Sharif Digital Repository

This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented. © 2007 IEEE  

This paper presents a simulation-based study of the stuck-open fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting stuck-open faults in these logic families. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented. © 2007 IEEE  

AC motor drive systems are sensitive to faults occurring at the power inverter, or at the control system. A novel fault tolerant Field Oriented Control system for induction motors is introduced. The system maintains speed control in the event of sensors malfunction and adverse signal conditions, providing enhanced reliability. The system comprises four different flux estimators which are fused by a Fuzzy aggregation system in order to give a reliable estimate of motor flux. The proposed control system is an effective and easy to implement method giving a potential for motor drive reliability enhancement. © 2006 IEEE  

This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental... 

The size and speed of SRAM caches of embedded systems are increasing in response to demands for higher performance. However, the SRAM caches are vulnerable to soft errors originated from energetic nuclear particles or electrical sources. This paper proposes a new protected cache scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without... 

Data integrity of words coming out of the caches needs to be checked to assure their correctness. This paper proposes a cache placement scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The results obtained from simulating some standard... 

This paper presents an experimental evaluation of the effectiveness of the Master/Checker (M/C) architecture in a 32-bit Pentium® processor system using both power-supply disturbance (PSD) fault injection and software-implemented fault injection (SWIFI) methods. A total of 6000 faults were injected in the Master processor to measure the error detection coverage of the Checker processor. The results of the experiments with PSD fault injection show that the error detection coverage of the M/C architecture is about 66.13%, which is not quite effective. This low coverage depends on the high rate of Master processor hangs because of voltage fluctuation. The coverage increased to about 99.73% when... 

Induction motor parameter estimation is generally needed for such purposes as fault detection and the achievement of high dynamic performance drives. This paper is an attempt to use variable structure control (VSC) methodology for the on-line estimation of several significant mechanical and electrical induction motor parameters. The estimated parameters are rotor resistance, magnetizing inductance, stator resistance and viscous damping coefficient In this combined control/estimation method, we propose to apply field-oriented control to the non-linear model of induction motor, and then transform the model by Input-state linearization into canonical form. Application of variable structure...