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An on-line BIST technique for stuck-open fault detection in CMOS circuits

Moghaddam, E ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/DSD.2007.4341532
  3. Publisher: 2007
  4. Abstract:
  5. This paper presents a simulation-based study of the stuck-open fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting stuck-open faults in these logic families. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented. © 2007 IEEE
  6. Keywords:
  7. Architectural design ; Built-in self test ; Fault detection ; Microprocessor chips ; Switching circuits ; Switching theory ; Systems analysis ; Cmos circuits ; CMOS logic circuits ; Line testing ; Logic families ; Open faults ; Pattern generations ; Power overheads ; Simulation results ; Logic circuits
  8. Source: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007, Lubeck, 29 August 2007 through 31 August 2007 ; 2007 , Pages 619-625 ; 076952978X (ISBN); 9780769529783 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4341532