Sharif Digital Repository

The rapid growth in the supply chain of electronic devices has led companies to purchase Intellectual Property or Integrated Circuits from unreliable sources. This dispersion in the design to fabrication stages of IP/IC has led to new attacks called hardware Trojans. Hardware Trojans can bargain information, reduce performance, or cause failure. Various methods have been introduced to detect or prevent hardware Trojans. Machine learning methods are one of these. Selecting the type and number of input variables in the learning algorithm has an important role in the performance of the learning model. Some previous hardware Trojan detection studies have used structural gate-level features to... 

This paper adopts a holistic approach to stress detection issues in software and hardware phases and aims to develop and evaluate a specific low-power and low-cost sensor using physiological signals. First, a stress detection model is presented using a public data set, where four types of signals, temperature, respiration, electrocardiogram (ECG), and electrodermal activity (EDA), are processed to extract 65 features. Using Kruskal-Wallis analysis, it is shown that 43 out of 65 features demonstrate a significant difference between stress and relaxed states. K nearest neighbor (KNN) algorithm is implemented to distinguish these states, which yields a classification accuracy of 96.0 ± 2.4%. It... 

This article reports the development of a new smart electrocardiogram (ECG) monitoring system, consisting of the related hardware, firmware, and Internet of Things (IoT)-based web service for artificial intelligence (AI)-assisted arrhythmia detection and a complementary Android application for data streaming. The hardware aspect of this article proposes an ultralow power patch sampling ECG data at 256 samples/s with 16-bit resolution. The battery life of the device is two weeks per charging, which alongside the flexible and slim (193.7 mm times62.4 mm times8.6 mm) and lightweight (43 g) allows the user to continue real-life activities while the real-time monitoring is being done without... 

Fast fault detection and converter reconfiguration is necessary for fault tolerant doubly fed induction generator (DFIG) in wind energy conversion systems (WECS) to prevent further damage and to make possible the continuity of service. Extra sensors are needed in order to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A fault tolerant converter topology for this application is studied. Control and fault detection system are implemented on a single FPGA and Hardware in the Loop experiments are performed to evaluate the proposed detection scheme, the digital controller and the fault... 

To stay competitive in the new dynamic market having large fluctuations in product demand, manufacturing companies must use systems that not only produce their goods with high productivity but also allow for rapid response to market changes. Reconfigurable manufacturing system (RMS) is a new paradigm that enables manufacturing systems to respond quickly and cost effectively to market demand. In other words, RMS is a system designed from the outset, for rapid changes in both hardware and software components, in order to quickly adjust its production capacity to fluctuations in market demand and adapt its functionality to new products. The effectiveness of an RMS depends on implementing its... 

A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, which allows for a high-accuracy compensation in a short interval. In the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the primary synchronization signal detection. In addition, we... 

In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm... 

In this paper, some important circuit parameters of a monolayer armchair graphene nanoribbon (GNR) field effect transistor (GNRFET) in different structures are studied. Also, these structures are Ideal with no defect, 1SVGNRFET with one single vacancy defect, and 3SVsGNRFET with three SV defects. Moreover, the circuit parameters are extracted based on Semi Classical Top of Barrier Modeling (SCTOBM) method. The I-V characteristics simulations of Ideal GNRFET, 1SVGNRFET and 3SVsGNRFET are used for comparing with SCTOBM method. These simulations are solved with Poisson-Schrodinger equation self-consistently by using Non- Equilibrium Green Function (NEGF) and in the real space approach. The... 

Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redundancy is generally more preferable than hardware redundancy. However, hard real-time systems often use hardware redundancy to meet high reliability requirements of safety-critical applications. In this paper we propose a hardware-redundancy technique with low energy-overhead for hard real-time systems. The proposed technique is based on standby-sparing, where the system is composed of a primary unit and a spare. Through analytical models, we have developed an online energy-management method which uses a slack... 

Efficient hardware realization of spiking neural networks is of great significance in a wide variety of applications, such as high-speed modeling and simulation of large-scale neural systems. Exploiting the key features of FPGAS, this paper presents a novel nonlinear function evaluation approach, based on an effective uniform piecewise linear segmentation method, to efficiently approximate the nonlinear terms of neuron and synaptic plasticity models targeting low-cost digital implementation. The proposed approach takes advantage of a high-speed and extremely simple segment address encoder unit regardless of the number of segments, and therefore is capable of accurately approximating a given...