Sharif Digital Repository

This work proposes an automatic method to generate opti- mized redundant hardware accelerator with maximum reliabil- ity given a single behavioral description for High-Level Syn- thesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase... 

Emergence of instrumentation frameworks has vastly contributed to the software engineering practices. As the instrumentation use cases become more complex, complexity of instrumenting programs also increases, leading to a higher risk of software defects, increased development time, and decreased maintainability. In security applications such as symbolic execution and taint analysis, which need to instrument a large number of instruction types, this complexity is prominent. This paper presents an architecture based on the Pin binary instrumentation framework to abstract the low-level OS and hardware-dependent implementation details, facilitate code reuse in heavyweight instrumentation use... 

This paper introduces a novel robotic platform, called RASA (Robot Assistant for Social Aims). This educational social robot is designed and constructed to facilitate teaching Persian Sign Language (PSL) to children with hearing disabilities. There are three predominant characteristics from which design guidelines of the robot are generated. First, the robot is designed as a fully functional interactive social robot with children as its social service recipients. Second, it comes with the ability to perform PSL, which demands a dexterous upper-body of 29 actuated degrees of freedom. Third, it has a relatively low development cost for a robot in its category. This funded project, addresses... 

This paper introduces a novel robotic platform, called RASA (Robot Assistant for Social Aims). This educational social robot is designed and constructed to facilitate teaching Persian Sign Language (PSL) to children with hearing disabilities. There are three predominant characteristics from which design guidelines of the robot are generated. First, the robot is designed as a fully functional interactive social robot with children as its social service recipients. Second, it comes with the ability to perform PSL, which demands a dexterous upper-body of 29 actuated degrees of freedom. Third, it has a relatively low development cost for a robot in its category. This funded project, addresses... 

During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5,... 

In software programs, most of the time, there is a chance for occurrence of faults in general, and exception faults in particular. Localizing those pieces of code that are responsible for a particular fault is one of the most complicated tasks, and it can produce incorrect results if done manually. Semi-automated and fully-automated techniques have been introduced to overcome this issue. However, despite recent advances in fault localization techniques, they are not necessarily applicable to Android applications because of their special characteristics such as context-awareness, use of sensors, being executable on various mobile devices, limited hardware resources, etc. To this aim, in this... 

In software programs, most of the time, there is a chance for occurrence of faults in general, and exception faults in particular. Localizing those pieces of code that are responsible for a particular fault is one of the most complicated tasks, and it can produce incorrect results if done manually. Semi-automated and fully-automated techniques have been introduced to overcome this issue. However, despite recent advances in fault localization techniques, they are not necessarily applicable to Android applications because of their special characteristics such as context-awareness, use of sensors, being executable on various mobile devices, limited hardware resources, etc. To this aim, in this... 

Extremely efficient convolutional neural network architectures are one of the most important requirements for limited-resource devices (such as embedded and mobile devices). The computing power and memory size are two important constraints of these devices. Recently, some architectures have been proposed to overcome these limitations by considering specific hardware-software equipment. In this paper, the lightweight residual densely connected blocks are proposed to guaranty the deep supervision, efficient gradient flow, and feature reuse abilities of convolutional neural network. The proposed method decreases the cost of training and inference processes without using any special... 

This work presents some new optimization approaches to implementation of Medium Access Control (MAC) layer of IEEE 802.11 wireless networking protocol using general purpose DSP and gate array systems. Optimization starts at design level. The hardware/software partitioning of the MACs architecture is optimized in the sense of minimal implementation burden, while maintaining the system's functionalities and performance. The proposed partitioning and implementation technique obviates the use of any Real Time Operating System (RTOS), which leads to a simple, high speed, and low memory structure of the MACs software. Also, solutions such as using hash tables and pipeline processing are given and... 

Modular Neural Networks have had significant success in a wide range of applications because of their superiority over single non-modular ones in terms of proper data representation, feasibility of hardware implementation and faster learning. This paper presents a constructive multilayer neural network (CMNN) in conjunction with a Hopfield model using a new cost function to simulate the behavior of superconductive fault current limiters (SFCLs). The results show that the proposed approach can efficiently simulate the behavior of SFCLs. ©2006 IEEE  

This paper presents a behavioral-based error detection technique called control flow checking by execution tracing (CFCET) to increase concurrent error detection capabilities of commercial off-the-shelf (COTS) processors. This technique traces the program jumps graph (PJG) at run-time and compares it with the reference jumps graph to detect possible violations caused by transient faults. The reference graph is driven by a preprocessor from the source program. The idea behind the CFCET is based on using an external watchdog processor (WDP) and also the internal execution tracing feature available in COTS processors to monitor the addresses of taken branches in a program, externally. This is... 

Embedded systems have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-core processors, which are commonly used to design MC systems, bring out new challenges due to the process variations. Power and frequency asymmetry affects the predictability of embedded systems. In this work, variation-aware techniques are explored to not only improve the reliability of MC systems, but also aid the scheduling and energy saving of them. We leverage the core-to-core (C2C) variations to protect high-criticality tasks and provide full service... 

The ODYSSEY design methodology has been recently introduced as a viable solution to the increasing design complexity problem in the ASICs. It is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these methods are implemented in hardware; others are simply executed by a general purpose processor. One fundamental element of this methodology is a network on chip that implements method invocation for hardware-based method calls. However this network is prone to faults, thus errors on it may result into system failure. In this paper an architectural fault-tolerance enhancement to the ODYSSEY design... 

Normally, random number generators produce uniformly distributed values. In some cases, such as Monte Carlo simulation, non-uniform distributed values (e.g. exponential distribution and weibull distribution) are required. One way of producing non-uniformly distributed random values, is to add an extra hardware to a uniformly distributed random number generator. In this paper, three different methods are studied to generate exponential random values. These methods are based oft three algorithm of logarithm evaluating namely: CORDIC, Interpolation and Piecewise lookup table. The study is based on an experimental evaluation of the above methods, using FPGA chips, to compare the speed, hardware... 

This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The... 

We propose a no-go theorem by proving the impossibility of constructing a deterministic quantum circuit that iterates a unitary oracle by calling it only once. Different schemes are provided to bypass this result and to approximately realize the iteration. The optimal scheme is also studied. An interesting observation is that for a large number of iterations, a trivial strategy like using the identity channel has the optimal performance, and preprocessing, postprocessing, or using resources like entanglement does not help at all. Intriguingly, the number of iterations, when being large enough, does not affect the performance of the proposed schemes  

In this paper, important issues that could come up in practice of Active Disturbance Rejection Control (ADRC) due to a common assumption and some inevitable practical restrictions are investigated. The main idea behind ADRC is modeling effects of both internal uncertainties and external disturbances as an extra state called the total disturbance which is timely estimated. In the majority of recent works, it is assumed that time derivative of total disturbance is bounded. First we prove that, beside the system characteristics, the validity of this assumption strongly depends on the tuning parameters, even in the case of simple classes of linear second order systems. Thus, one should be... 

This paper proposes a deep deterministic policy gradient (DDPG) based nonlinear integral backstepping (NIB) in combination with model free control (MFC) for pitch angle control of variable speed wind turbine. In particular, the controller has been presented as a digital twin (DT) concept, which is an increasingly growing method in a variety of applications. In DDPG-NIB-MFC, the pitch angle is considered as the control input that depends on the optimal rotor speed, which is usually derived from effective wind speed. The system stability according to the Lyapunov theory can be achieved by the recursive nature of the backstepping theory and the integral action has been used to compensate for...