Sharif Digital Repository

The series configuration of fast semiconductor switches seems to be the key component in the high-voltage and fast rising time pulse generation. In this approach, two important issues must be considered. The first is to provide a safe operating condition for the switches in transient intervals. The second is to design a gate drive system with the capability of driving a large number of discrete devices simultaneously. The aim of this paper is to obviate these two requirements. First, different factors affecting the unbalanced voltage sharing between the series switches are discussed. In this investigation, the switch-to-ground parasitic capacitance effect has been recognized as the major... 

Wireless Nano-scale Sensor Networks (WNSNs) are very simple and energy restricted networks that operate over terahertz band ranging from 0.1-10 THz, which faces significant molecular absorption noise and attenuation. Given these challenges, reliability, energy efficiency, and simplicity constitute the main criteria in designing communication protocols for WNSNs. Due to its simplicity and energy efficiency, carrier-less pulse based modulation is considered the best candidate for WNSNs. In this paper, we compare the performance of four different carrier-less modulations, PAM, OOK, PPM, and BPSK, in the context of WNSNs operating within the terahertz band. Our study shows that although BPSK is... 

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of... 

System fault-tree analysis is a technique for modeling dependability that is in widespread use. For systems such as embedded systems that include both hardware and software, the integration of hardware and software fault trees has proved problematic. In this paper, we present a method for reliability and safety analysis of embedded systems modeled by SystemC language. The evaluation is based on the fault trees generated from both hardware and software parts of the embedded systems described in the unified language. The unified modeling of both hardware and software of embedded systems using SystemC enables designers to be early aware from the safety and reliability of their designs more... 

FPGA-based multiprocessors, referred as softmultiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in the configuration bits. The main of this method is to analyze the scheduled task graph and select a subset of tasks to be replicated in multiple processors based on the utilization of the processors in different execution phases. To this end, 1) errors are detected by re-executing a subset of tasks... 

This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity additions and comparisons. The VLSI implementation uses a pipelined architecture that produces an LR-reduced matrix every 40 cycles, which is a 60% reduction compared to current implementations. The proposed design was synthesized in both 130μm and 65nm CMOS resulting in clock speeds of 332MHz and... 

In this paper, a decentralized controller for trajectory tracking of modular and reconfigurable robot manipulators is developed. The proposed control scheme uses joint-torque sensory feedback; also sliding mode control is employed to make both position and velocity tracking errors of robot manipulators globally converging to zero. Proposed scheme also guarantees that all signals in closed-loop systems will be bounded. In contrast to some of prior works in this scheme, each controller uses a smooth law to achieve its purposes. In this method, each controller uses only local information for producing control law hence separated controller can be used to control each module of manipulator and... 

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy... 

Recent developments in improving lighting efficiency and cost reduction of LEDs have made them suitable alternatives to the current lighting systems. In this paper, a novel offline structure is proposed to drive LEDs. The proposed circuit has a high-input power factor, high efficiency, a long lifetime, and it produces no flicker. To increase the lifetime of the converter, the proposed circuit does not include any electrolytic capacitors in the power stage. The proposed circuit consists of a transition mode flyback converter in order to improve power factor. Additionally, a buck converter is added to the third winding of the flyback transformer in order to create two parallel paths for the... 

In this paper, a hardware control flow checking technique is presented and evaluated. This technique uses reconfigurable of the shelf FPGA in order to concurrently check the execution flow of the target micro processor. The technique assigns signatures to the main program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. The main characteristic of this technique is its ability to be applied to any kind of processor architecture and platforms. The low imposed hardware and performance overhead by this technique makes it suitable for those applications in which cost is a major concern, such as... 

Optical coherence tomography (OCT) is a noninvasive imaging modality that provides cross-sectional images from microstructures of tissues. This optical imaging system works based on Michelson interferometry principle and has intermediate resolution and penetration depth which makes it appropriate for imaging thin tissues such as skin and eye. OCT images suffer from three main artifacts that make images difficult to be analyzed. The first one is small grainy structures called speckle which degrade image quality and decreases axial and lateral resolution. The second one is light intensity attenuation which is a function of depth. It happens because of absorbing and scattering nature of tissue... 

In conventional arrays, improving angular resolution requires larger aperture which demands more number of elements. On the other hand, array thinning is an efficient method of achieving narrow beamwidth (high angular resolution) with fewer number of elements. Reducing the number of elements results in reducing weight, cost, hardware complexity, and energy consumption. In this paper, a novel dynamic programming algorithm of array thinning with the objective of reducing sidelobe levels (SLLs), desired for large circular arrays, is proposed. The circular array is partitioned into annular rings, and the objective of the optimization problem is to determine the number of active elements in each... 

Normally, random number generators produce uniformly distributed values. In some cases, such as Monte Carlo simulation, non-uniform distributed values (e.g. exponential distribution and weibull distribution) are required. One way of producing non-uniformly distributed random values, is to add an extra hardware to a uniformly distributed random number generator. In this paper, three different methods are studied to generate exponential random values. These methods are based oft three algorithm of logarithm evaluating namely: CORDIC, Interpolation and Piecewise lookup table. The study is based on an experimental evaluation of the above methods, using FPGA chips, to compare the speed, hardware... 

A 3 DOF platform was constructed in the Georgia Institute of Technology to perform new control strategies in an experimental framework. Also in this simulator, there isn't any sensor used by a real satellite for attitude determination. The setup was structured on data transmitting and synchronization of distributed elements for ADCS tests. In such a plan, not only can different elements of the test bed be used individually, but also they can support an integrated hardware in the loop test. Accordingly, reusing the hardware sources causes a cost reduction of development. Furthermore the geometric interferences of different parts are minimized in this plan. So, the test bed can be developed... 

ALM is an adaptive recursive algorithm which tries to express a multi-input multi-output system as a fuzzy combination of some single-input single-output systems. It uses a fuzzy curve fitting technique for behavior extraction or finding the input-output transfor-mation of each of the single-input single-output systems, which called ink drop spread (IDS). In this paper we present a new implementation of a hardware unit implementing the ink drop spread (IDS) method  

Disk traces are typically used to analyze real-life workloads and for replay-based evaluations. This approach benefits from capturing important details such as varying behavior patterns, bursty activity, and diurnal patterns of system activity, which are often missing from the behavior of workload synthesis tools. However, accurate capture of such details requires recording traces containing long durations of system activity, which are difficult to use for replay-based evaluation. One way of solving the problem of long storage trace duration is the use of disk simulators. While publicly available disk simulators can greatly accelerate experiments, they have not kept up with technological... 

With the increasing popularity of cloud computing services, the more number of cloud data centers are constructed over the globe. This makes the power consumption of cloud data center elements as a big challenge. Hereby, several software and hardware approaches have been proposed to handle this issue. However, this problem has not been optimally solved yet. In this paper, we propose an online cloud resource management with live migration of virtual machines (VMs) to reduce power consumption. To do so, a prediction-based and power-aware virtual machine allocation algorithm is proposed. Also, we present a three-tier framework for energy-efficient resource management in cloud data centers.... 

Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core... 

Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture...