Sharif Digital Repository

This paper presents the design and implementation of a distributed class-J power amplifier (DJPA) in a 0.25-μm AlGaAs-InGaAs pHEMT technology. Class-J mode of operation is introduced in design of distributed power amplifiers (DPAs) to achieve high power added efficiencies (PAEs) over wide frequency ranges. Extensive load-pull (LP) and source-pull (SP) simulations are performed to show that class-J PAs are less sensitive to proper termination of higher order harmonics, and high PAE and output power can be obtained even if the second, third, fourth, and fifth harmonics comprise a real impedance. This is essential in DPAs as the higher order harmonics of the frequencies at lower side of the... 

In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply. © 2007 IEEE  

A new level converter for use in dual voltage SOI digital circuits is presented. The technique which uses the idea of keeper transistors, consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations  

An 8-bit High-speed folding/interpolating ADC is presented. Designed in 0.18μm CMOS technology, the ADC dissipates only 50mW from a single 1.5V supply. A novel technique based on using both N and P folding cells is used to widen the input range and a self-calibration technique based on using Trimmable MOSFETs is employed to improve the static and dynamic performance  

A novel, precision current reference with low temperature and supply sensitivity and without any external component has been designed in a 0.18μm CMOS mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit like a beta multiplier. The simulation results show max-to-min fluctuation of about 1% over a temperature range of -20°C to +100°C and supply voltage range of 1.1V to 2V with ±30% tolerance for all of the used on-chip resistors. The maximum nominal current variation in process corners is less than 3.5%. © 2003 IEEE  

A traveling wave distributed mixer is studied. It is shown that increasing the drain-source capacitances in a distributed FET mixer simultaneously improves its conversion gain and noise figure. Besides, it is shown that proper loading of input and output elements can improve the device performance. The simulation results are well matched with the measurements and also with the results of the existing certified simulators. © 2002 IEEE  

This paper presents a broad-band bandpass filter (BPF) designed as a channel-select filter for wireless applications. It is implemented as a low-pass filter (LPF) in series with a high-pass filter (HPF) for lower power consumption compared to true BPF. Semiscaling of the filter nodes is superior in the wireless receiver over traditional full scaling. The HPF is built with low-pass feedback of an amplifier. The bandwidth is selectable from 625 kHz, 2.5 MHz, or 10 MHz. The filter stopband loss is more than 50 dB extending beyond 100 MHz, and passband ripple less than 2.5 dB. Fabricated in a 0.6-μm CMOS process, it provides a minimum input noise of 16 nV/√Hz noise with 22.5-dBm out-of-band... 

A new approach for the design of two-stage Miller-compensated CMOS op amps is presented. The paper studies the basic relations between power consumption, unitygain bandwidth, the biasing region, technology parameters, and the external capacitive load. As a result, simple and efficient design guides are provided to achieve the minimum possible power consumption for the given specifications and for short-channel devices. It is shown that the conventional design procedures do not always result in minimum power op amps. The presented results are also verified by Spectre simulations  

A method to design a tunable low noise amplifier (LNA) for multiband receivers is proposed. This paper also presents a single-ended to differential conversion (S2DC) topology which improves the LNA linearity without degrading its noise performance. Combining input tuning with S2DC in a single stage reduces power consumption of the LNA and decreases effects of supply noise. An LNA has been designed based on the proposed method for 2.3-4.8 GHz in a 0.18 μm CMOS technology. Simulations show an IIP3 of -3.2 dBm, a less than 3.7 dB noise figure (NF), a voltage gain of 24 dB in the whole frequency range. The LNA draws 13.1 mW from a 1.8 V supply. The results indicate that the proposed tuning... 

Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in... 

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm... 

In recent years, the security of integrated circuits (ICs) has received more attention as usage of ICs made by untrustworthy foundries has increased in safety-critical systems [1]. In this paper, we introduce a novel approach for fingerprinting the delay of functional paths in a sequential circuit that have millions of transistors, like processors. We present a method for inserting Ring Oscillators (ROs) into scan chain for measuring the delay of each functional path inside the chip. Using the proposed method, the payload part of Trojans will be detected according to their size and cell types. Our method can be used by power-based Trojan detection approaches for finding the trigger part of... 

A CMOS fully differential UHF variable gain amplifier for use in a direct-conversion DVB-H receiver is presented employing input devices with variable aspect ratios. High linearity is achieved by reducing the transconductance of the input transistors for lower gain settings. It is shown that this technique has better linearity and noise performance compared to the conventional methods in which the gain reduction is performed at preceding stages. Implemented in TSMC 0.18-μm CMOS process, the inductorless RF VGA covers a voltage gain ranging from 15.5 dB to -6.5 dB with a maximum IIP3 of +24 dBm. The amplifier achieves a 3-dB bandwidth of 1.4 GHz and a minimum noise figure of 5.8 dB while... 

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB... 

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 μ m CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from... 

To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM cell using same design rules. Simulation result in standard 0.25μm CMOS technology shows purposed cell has correct operation during read/write and idle mode. The average delay of new cell is 20% smaller than a six-transistor SRAM cell. © 2008 IEEE  

In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

Future System-on-Chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the Intellectual Properties (IPs). Designing and optimizing SoCs is an increasingly difficult task due to the size and complexity of the SoC design space, high cost of detailed simulation, and several constraints that the design must satisfy. For efficient design of SoCs, an efficient mapping of IPs onto Networks-on-Chip (NoCs) is highly desirable. Towards this end, we have presented PERMAP, a PERformance-aware MAPping algorithm which maps the IPs onto a generic NoC architecture such that the average communication delay is minimized. This is... 

Multilevel interconnect network of a macrocell for 7.5 nm technology node is designed with carbon based interconnects (CBI) and Cu. Results are compared. Constrains of using CBI is discussed. It is shown that by using CBI power dissipation associated with wires could decrease by 32%. To use GNRs for more than one metal pair, reverse wire pitch idea is proposed that prevents undesirable increase in the number of metal layers