Sharif Digital Repository

Design techniques to enhance bandwidth and linearity of broadband multistage low-noise amplifiers (LNAs) are presented. A feedback amplifier circuit is proposed to compensate for transistor gain roll-off with frequency in other amplifier stages and extend overall bandwidth. Moreover, a transistor width tapering in a multistage LNA is applied to improve linearity. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA implemented in a 0.1-μm GaAs pHEMT process. The LNA features 18-43 GHz bandwidth, 21.6 dB average gain, and 1.8-2.7 noise figure (NF). It exhibits output 1-dB compression point of 11.5 dBm at 30 GHz and consumes 70 mA bias current from a... 

This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence of nonlinear drain-source resistance of transistors (RDS). A procedure is developed for ideal transistor sizing where transistors are concurrently stabilized and sized to achieve the maximum power-added efficiency (PAE). A 3.5-7 GHz, 0.5-W class-J PA is implemented in a 0.1-μm AlGaAs-InGaAs pHEMT technology to check the accuracy of the proposed approach. With chip dimensions of 1.57 × 1.29 mm2, the PA achieves 56% average PAE over the frequency... 

This paper presents a methodology for the design of Ka/Q-band monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs). Design techniques are introduced to reduce chip area and to improve bandwidth (BW). These techniques are applied to the design of a 31-39-GHz 5-W HPA implemented on a 0.1-μm AlGaAs-InGaAs pseudomorphic HEMT (pHEMT) technology. With chip dimensions of 3.35 × 3.2 mm2, the HPA achieves 24% average power-added efficiency (PAE) over the frequency band, while maintaining an average 22-dB small-signal gain. A balanced high-power amplifier (BPA) is also presented, which combines the power of two 5-W HPA cells to deliver peak 8.5-W output power (Pout) in the... 

The analysis and design of a tunable low noise active inductor is presented. The noise performance of the proposed gyrator-based active inductor is improved without either degrading its quality factor or consuming more power using a linear Feed Forward Path (FFP). The proposed low noise active inductor has been designed and fabricated using standard 0.18-μm CMOS technology. The measurements show a 3 fold improvement in the input noise current compared to that of conventional active inductors. The active inductor was tuned and measured at the resonance frequency of 2.5 GHz, which could be extended as high as 5.5 GHz, with a quality factor of 30. The circuit draws 4.8 mA from a 1.8 V supply  

This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,... 

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

In this paper a strategy is proposed for compressing the test data while using concurrent hybrid-BIST methodologyfor testing SoCs. In the proposed method, in addition tousing BIST strategy for testing cores with deterministic sequential test patterns in an SoC( Without using scan chains), (ATE) is used for testing cores with deterministic test patterns through Test Access Mechanism (TAM) or functional bus. As will be shown in experimental results, this process compresses hybrid-BIST overall test patterns considerably that affects the overall Test Application Time (TAT) in comparison with pure deterministic, pure pseudo random, and combination of deterministic and pseudo random test patterns  

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V  

A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology  

In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and... 

Cryogenic technologies not only improve the performance of interconnects but also the performance of transistors and consequently drivers and repeaters. Although in cryogenically cooled integrated circuits the local temperature of interconnects and transistors may be as low as 50 K, it may easily reach to 600 K in high-temperature chips. In this brief, we investigated the impact of temperature on the delay of local, intermediate, unit-repeater-inserted (URI), and cascaded repeater-inserted (CRI) global copper interconnects for minimum technology node with available transistor model (32-nm technology). Our results show that temperature variation of driver resistance could change the delay of... 

Cryptographic computation exploits finite field arithmetic and, in particular, multiplication. Lightweight and fast implementations of such arithmetic are necessary for many sensitive applications. This brief proposed a low-complexity systolic Montgomery multiplication over GF(2m). Our complexity analysis shows that the area complexity of the proposed architecture is reduced compared with the previous work. This has also been confirmed through our application-specific integrated circuit area and time equivalent estimations and implementations. Hence, the proposed architecture appears to be very well suited for high-throughput low-complexity cryptographic applications  

In recent years, hardware Trojans (HTs) have become one of the main challenging concerns within the chain of manufacturing digital integrated circuit chips. Because of their diversity in chips, HTs are difficult to detect and locate. This paper attempted to propose a new improved method for detection and localization of HTs based on the real-time logical values of nodes. The algorithm extracts the nodes with special attributes. At the next stage, the nodes with the greatest similarity in terms of logical value are selected as targets. Depending on the size of the circuit, the extraction continues until a sufficient number of similar nodes has been selected. The logical relationship between... 

The effect of dielectric cladding on the waveguiding characteristics of an array of metallic pillars on a metal plane in the sub-terahertz band is explored. Firstly, a 2D structure made up of a metallic grating of infinite lateral width with various dielectric overlays is analytically studied to get more insight into the problem. Then the ideas inferred from the 2D structure are applied to the realistic 3D structure that has a finite lateral width. It is shown that by proper design of the dielectric medium surrounding the metallic structure the modal field confinement can be enhanced in a broad frequency band resulting in a low bending loss. Especially, by integrating the pillars into a...