Sharif Digital Repository

Applying conventional dc-voltage-based droop approaches for hybrid ac/dc microgrids interconnected by a single interlinking converter (IC) can properly manage the power flow among ac and dc subgrids. However, due to the effect of line resistances, these approaches may create a circulating power as well as overstressing the ICs in the case of employing multiple ICs for interconnecting the ac and dc subgrids. This paper proposes an autonomous power sharing approach for hybrid microgrids interconnected through multiple ICs by introducing a superimposed frequency in the dc subgrid. Hence, a suitable droop approach is presented to manage the power among the dc and ac sources as well as ICs. The... 

This paper presents a capacitor cross-coupled gm-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13 μm CMOS technology illustrates near 1.7 dB improvement in the circuit sensitivity and 5.2 dB enhancement in transimpedance gain compared to its... 

A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25-4.75 GHz band designed for low power and high data rate communication is implemented in 0.18 μm CMOS technology. When operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8 V supply [1]. Compared to UWB transceivers reported in the literature, this chip dissipates the lowest energy per bit. In addition, the combination of the frequency channelized architecture, high-linearity RF circuits, aggressive baseband filtering, and low local oscillator spurs results in an interference-tolerant receiver that is able to co-exist with systems operating... 

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch... 

A fully integrated, low-cost (area), low-power, high-gain, differential Optical Receiver Analog Front-End (AFE), including Transimpedance Amplifier (TIA), Limiting Amplifier (LA), DC-Offset Cancellation Feedback and Output-Buffer is designed in TSMC 0.18μm CMOS Technology. The optimized TIA has a Regulated Cascode (RGC) topology, with 5.9mW power-dissipation, 48 dBΩ gain, 8.46GHz bandwidth. The Proposed Limiting Amplifier (LA) has an Inductor-Less topology, with 41.9dB gain, 91.1mW power consumption (including Output Buffer), output swing of 0.4VP-P, and bandwidth of 7.88GHz (Output-Buffer applied), using Built-in Active Inductors and Negative Miller Capacitance to broaden the bandwidth. The... 

High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the various trade-offs between two of these objectives. However, as we will argue later, the three design objectives should be considered jointly and simultaneously. The first aim of this paper is to analyze the impact of various error-control schemes on the simultaneous trade-off between reliability, performance and energy when voltage swing varies. We provide a detailed comparative analysis of the error-control schemes using analytical models and SPICE simulations. The second aim of this paper is to analyze the impact of... 

This paper presents a method for emulating switch-level models of CMOS circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. The method presented in this paper, unlike the abstraction methods, can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach... 

Design of a novel RF front - end structure for 2450-MHz Band IEEE 802.15.4 ZigBee standard in a 0.18-μm CMOS process is presented. Utilizing a common-gate structure instead of conventional inductive degenerated common source amplifier, Low noise figure is achieved with LNA bias current as low as 1mA. An analytical method is presented to minimize the Noise figure of proposed common-gate LNA structure. Together with the LNA, an active Gilbert Cell mixer is adopted to convert the RF signal to 2MHz IF signal. Employing an enhanced current re-use structure, simulation results show a conversion gain of 37.7dB, a Noise figure of 5.9dB and an IIP3 of -4dBm for the front -end. The RF front - end... 

The design of a power-efficient second-order Δ/∑ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. © Springer Science + Business Media, LLC 2006  

We have investigated the rf SQUID (radio-frequency superconducting quantum interference device) and its coupling to tank circuit configurations to achieve an optimal front-end assembly for sensitive and high spatial resolution magnetic imaging systems. The investigation of the YBCO rf SQUID coupling to the conventional LC tank circuits revealed that coupling from the back of the SQUID substrate enhances the SQUID signal while facilitating the front-end assembly configuration. The optimal thickness of the substrate material between the SQUID and the tank circuit is 0.4 mm for LaAlO3 resulting in an increase of the SQUID flux-voltage transfer function signal, Vspp, of 1.5 times, and 0.5 mm for... 

The ODYSSEY design methodology is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these method calls are implemented in hardware functional units, while others are simply executed by a general-purpose processor. There is a communication overhead because functional units must communicate with each other and with the processor core. In this paper we utilize the custom instructions capability of Nios II processor to enhance the performance of our ASIP. Since these instructions are in the processor itself, there will be no communication overhead for using them. We analyze the performance of the... 

A 1.8V, 10-Bit, 40-MS/s Pipeline analog-to-digital converter designed using 0.18-μmCMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free- dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5mW.... 

In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1-1.5V and Vth=0-0.8V, are analyzed to find optimal Vdd and Vth BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and... 

A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the bias circuit is presented. A 1.8v 2.4GHz differential LC VCO is designed in a 0.18u CMOS technology using this technique. With the proposed switching technique, the close in phase noise is improved as much as 15dB at 500 kHz offset. The simulated phase noise at the offsets of 500 kHz and 1 MHz is... 

Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. In our register allocation method, several high-level testability parameters including sequential depth, sequential loop, and controllability/observability are considered. Our experiments show using this register allocation method results in significant improvement in automatic test pattern generation time... 

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS LC oscillator is discussed. The phase noise performance for this kind of oscillator is predicted by using a simplified model. This method enables us to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the presented method is demonstrated by designing an LC CMOS oscillator in a 0.24μm CMOS technology. The predictions obtained from the derived expressions are in good agreement with simulation results over a wide range of the supply voltage. © 2004 IEEE  

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045 μm2 silicon area. © 2005 IEEE  

This paper presents a zero-voltage switching current mode sample and hold(S/H) circuit. The proposed S/H has 12 bit linearity at 180MHz sampling rate for 1.5v supply voltage. The S/H circuit is designed for 0.18μm CMOS technology  

A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power  

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a...