Sharif Digital Repository

In this work, the wind farm layout optimization problem is dealt with using a new approach. The aim of wind farm layout optimization is to maximize the output power of a wind farm considering the wake losses. Layout optimization minimizes the wake losses regarding the location of the turbines. Three different wind scenarios with different wind direction angles, wind direction blowing probabilities, and Weibull distribution parameters are assumed. Since, the problem is nonlinear and constrained, imperialist competitive algorithm is used as a modern and powerful algorithm for continuous optimization problems. The optimization outcomes indicate that imperialist competitive algorithm yields... 

An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using... 

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

A new switching method for the stabilisation of a one-dimensional capacitor array tank for the stepwise charging of a load capacitor is presented. In this method, the tank capacitor configuration is rearranged in a circular manner once the charging process of a load capacitor finishes and before the charging process of a new load capacitor begins. Unlike previously reported methods, this method does not require backward switching for the stabilisation of tank capacitor voltages. Hence, the proposed method reduces the number of charging process steps by a factor of up to 2 compared with the conventional method. Moreover, since the tank recycles its charge inherently, the capacitive load can... 

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this method, the SACs are modeled as a discrete time system. Unlike previous methods, the stability is verified for arbitrary load capacitor ratios. Moreover, this method presents analytical derivations to offer an area/energy efficient design methodology. MATLAB simulations, post-layout simulations in the CMOS 0.18 μm technology, silicon measurements, and measurements based on discrete components confirm the precision of the analytical derivations. Using the proposed design methodology, a capacitive tank has been designed which reduces the energy consumption by 20% while the total size of the tank... 

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching... 

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

A low-power technique for high-resolution comparators is introduced. In this technique, p-type metal-oxide-semiconductor field-effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter-based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n-channel metal-oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power... 

Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed scheme, we identify the unused resources at the device layout-level and offer dummy logic cells for different resources. The proposed HTH protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that by employing the proposed HTH... 

This study presents a new approach for designing optimal sensors layout based on accuracy of defect mapping. It is obtained from combination of the reference-free damage detection technique and the probability-based diagnostic imaging method. Considering damage indices based on continuous wavelet transform of sensors signals, the core of this study involves with development of a database of continuous wavelet transform features of a crack. In fact, the database contains the data from 594 different states in crack positions, orientations, and the considered sensing path lengths. Eventually, this database is used for localization of damage by interpolating the stored data collected from the... 

Optimization of wind farm (WF) layout has been studied in the literature with the objective of maximizing the wind energy capture. Based on the power spectrum density (PSD) theorem, this paper shows that the WF layout affects not only the total harvested energy but also the level of power fluctuation, which in turn influences required capacity of battery energy storage system (BESS) needed to mitigate the inherent power fluctuation of the wind farms. Since both harvested energy level and BESS capacity directly influence the profit of WF owner, the effect of WF layout on these quantities are taken into account simultaneously and WF layout optimization problem is redefined. Genetic algorithm... 

Optimization of wind farm (WF) layout has been studied in the literature with the objective of maximizing the wind energy capture. Based on the power spectrum density theorem, this paper shows that the WF layout affects not only the total harvested energy but also the level of power fluctuation, which, in turn, influences required capacity of battery energy storage system (BESS) needed to mitigate the inherent power fluctuation of the WFs. Since, both harvested energy level and BESS capacity directly influence the profit of WF owner, the effect of WF layout on these quantities is taken into account simultaneously, and WF layout optimization problem is redefined. Genetic algorithm is then... 

A large-signal linearization method for operational transconductance amplifiers (OTA) using a combination of cross-coupled quadratic cell and a novel non-linear current injection technique is presented in this paper. Post-layout simulations show that for 180 nm CMOS process with a 1.8 V power supply, total harmonic distortion (THD) at 1.5 V peak-to-peak and 5 kHz input is less than −46 dB. Also, the dynamic range (DR) at given THD is 68 dB with power consumption of 0.64 mW. To verify the performance, the proposed OTA is used to design a new configurable filter in high-frequency range using N-path filter methodology. Universal Butterworth Gm-C active filters are embedded in the proposed... 

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is... 

Solving the facility layout problems by graph theory consists of two stages. In the first stage, a planar graph that specifies desired adjacencies is obtained and in the second stage, a block layout is achieved from the planar graph. In this paper, we introduce face area as a new concept for constructing a block layout. Based on this idea, we present a new algorithm for constructing block layout from a maximal planar graph (MPG). This MPG must be generated from deltahedron heuristic. Constructed block layout by this algorithm satisfies all of adjacency and area requirements  

A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using... 

The Multi-Floor Layout Problem (MFLP) is the problem of finding the position of each department in a plant floor in a multi-floor building without any overlapping between departments in order to optimize a particular objective function, more commonly the sum of the material handling costs. In this paper, a special class of MFLP, called Uncertain Multi-Floor Discrete Layout Problem (UMFDLP), is defined. In this problem, a multi-floor building is considered in which an underground store is utilized to contain main storages, and different departments can be located in the other floors in potential pre-determined locations. Furthermore, all material flows are not constant. Moreover, the...