Sharif Digital Repository

Network on chips (NoCs) have emerged as a feasible solution to handle growing number of communicating components on a single chip. The scalability of chipsincreases the probability of errors and making the reliability a major issue in scaling chips. Soft errors and crosstalk faults are the most important fault sources which can decrease the reliability of NoCs. The probability of Soft errors has increased by about 6 to 7 times by scaling from 130 to 30 nm technology. Since buffers occupy in about 40% to 90% of the area of switches, the probability of a multiple bit upset in a switch buffers is noticeable. In NoC architecture, a packet is broken down into multiple flow control units called... 

Growth in the number of transistors on a single die has made Network-on-Chips more vulnerable to transient faults such as Crosstalks, SEUs and MBUs. The aim of this thesis is to evaluate the effects of virtual channel structures on the performance and the power consumptions of NoCs in the presence of transient faults. Evaluations have been carried out by different switch architectures and experimental conditions, i.e., different traffic and fault injection rates. In this regard, we have measured the power and latency of the switch both in different buffer allocation mechanisms and different switching methods. The evaluated switching methods in this work vary from Virtual Cut through (VCT) to... 

The fast development of semiconductor industry has moved the design methodology to SoC (System on Chip) design. This growing trend has made it possible to perform parallel processing on a chip. Due to the increasing number of processing elements In SoCs, buses become the bottleneck of the system and lead to non-efficient designs. In the early years of the current decade, Network on Chip (NoC) was introduced and considered by the researchers. NoC is an efficient solution that eliminates bus bottleneck and it had been introduced as a suitable substructure for interconnecting processing elements. The NoCs were originally built based on Interconnection Networks. Although initially aimed at... 

With increasing number of processors on a chip, the role of interconnections becomes more important in both power consumption and bandwidth. As a result, in MultiProcessor System-on-Chip architectures, the design constraints will shift from "Computational Constraints" to "Communicational Constraints". Nowadays, optical information transfer is introduced as a suitable substitution for electrical interconnections in chips, which can eliminate their problems. Many different optical networks have been presented so far. These networks can be divided into two subcategories. Networks of the first category use an electrical infrastructure as well as optical one. Hence, the scalability of scheme is... 

As the number of processing cores on a single chip continues to grow, the need for a high bandwidth, low power communication structure, will be the most important requirement of the next generation chip multiprocessors. Today, a major part of power consumption in multicore architectures belongs to interconnects. Due to these facts, reducing power consumption, as well as supporting high performance, is of major concern in these architectures. Optical interconnects have the potential to replace electrical wires to solve the bottleneck of communications in integrated circuits. Various routers and architectures with different points of view, have been recently designed considering existing... 

Heterogeneity is one of the challenges in the current NoC (Network-on-Chip) domain which oblige designers to consider less regular topologies to provide the best cost-performance trade-off while minimizing resource and power consumption and providing the maximum flexibility. Irregular mesh is a topology which combines the benefits of regularity and advantage of irregularity. Another important issue in any NoC is the selection of routing algorithm which provides the best performance. Routing algorithms especially those coupled with wormhole switching should deal with deadlock occurrences. Deadlock detection and recovery-based routing schemes for this type of switching gained attraction since... 

Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. An L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets through a simple-yet-effective predictor. Upon the occurrence of an L1-D miss, the predictor identifies the LLC slice that will serve the next L1-D miss and a circuit will be set up for the upcoming miss request to accelerate its transmission. When the upcoming miss occurs, the resulting request can use the already... 

It is now possible to integrate hundreds of modules (e.g. processors, memories) in a single silicon die. Handling the communication requirements between such modules by interconnecting them using shared buses is not possible from the performance point of view. One of the solutions is to use a network-on-chip (NoC) based communication infrastructure. NoCs were shown to be effective for solving the global interconnection problem among modules. These architectures emphasize the separation between computing and communication, and guarantee a good degree of design reuse and scalability. Mesh topology is favored by many researchers as the topology of NoCs because of its layout efficiency.... 

Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

With the advance of the semiconductor technology, it has been feasible now to fabricate high performance multiprocessor systems-on-chips, containing tens and in the near future hundreds of processing cores. Meanwhile, the diminished technology feature size and high power consumption limit in using previous communication structures such as shared buses. Networks-on-Chip (NoC) have been introduced to obviate these constraints by providing high modularity, scalability and inherent parallelism. Design of these interconnect structures includes multiple tradeoffs between delays, throughput, energy consumption and silicon area requirements. So far, many mechanisms have been proposed to improve the... 

NOCs contribute to a large portion of a many-core SOC power consumption. A significant fraction of the mentioned power consumption is due to the buffers, crossbar and the links. Thus, in this thesis, a new method would be introduced which reduces the power consumption of the NOCs in large scale. This method utilizes the latency asymmetry of router pipeline stages for dynamic power reduction and uses different voltage swings for buffers, links and the crossbar in order to decrease the dynamic power consumption while maintaining the performance. Moreover, since the static power consumption has gained a noticeable importance in recent years, a method for degrading this power component is also... 

CPU-GPU Heterogeneous System Architectures (HSA) play an important role in today's computing systems. Because of fast-growing in technology and the necessity of high-performance computing, HSAs are widely used platforms. Integrating the multi-core Central Processing Unit (CPU) with many-core Graphics Processing Unit (GPU) on the same die combines the feature of both processors and providing better performance. The capacity of HSAs to provide high throughput of computing led to the widespread use of these systems. Besides the high performance of HSAs, we also face challenges. These challenges are caused by the use of two processors with different behaviors and requirements on the same die.... 

Deep Neural Networks (DNNs) are widely used as a promising machine learning method in different applications and come with intensive computation and storage requirements. In recent years, several pieces of prior work have proposed different accelerators to improve DNNs processing. We observe that although the state-of-the-art DNN accelerators effectively process some network layers of certain shapes, they fail to keep computation resources fully utilized for many other layers. The reason is twofold: first, the mapping algorithm is unable to employ all compute cores for processing some layer types and dimension sizes, and second, the hardware cannot perform data distribution and aggregation... 

The advancement of technology in the semiconductor industry and the resulting increase in the number of transistors on a chip has led to an increase in the number of processing cores an increase in the number of processing cores in a system on chip (SoC). A surge in the number of processing cores, makes their communication more and more noteworthy. This communication is established through the network on chip (NoC). One of the main challenges in NoC design is power management, as it constitutes a high percentage of the overall power consumption of the chip. One of the most power-hungry components of NoC is the router. According to our observation, some of the components of the routers are... 

Technology node scaling in recent decades ushered in gate delay cut-off and rise of interconnection latency. Hence, interconnects have become a major performance bottleneck of high performance system-on-chips (SoC) and integrated circuits (IC). In addition, interconnectiosns have become more susceptible to noises in particular crosstalk. On the other hand, the advent of multi-core processors with ever increasing number of cores has highlighted the need for fast and reliable interconnections. One of the potential solutions to alleviate the interconnection delay problem is the three dimensional integration using through-silicon vias (TSV). Vertical integration of IC dies using TSVs offers high...