Sharif Digital Repository

Many fully-adaptive algorithms have been proposed to overcome the performance limitations of deterministic routing in networks used in high-performance multicomputers, such as the well-known regular n-D torus. This paper proposes a simple yet reasonably accurate analytical performance model to predict message communication latency in tori networks. This model requires a running time of O(1) which is the fastest model yet reported in the literature. Extensive simulations reveal that the new performance model maintains a reasonable accuracy when the network operates under different traffic conditions. The model is then used to perform an extensive investigation into the performance merits of... 

Network-on-Chips (NoCs) employ several virtual channels per input port to mitigate head-of-line blocking issue in transmitting network packets. Unfortunately, these virtual channels are power-hungry resources that significantly contribute to the total power consumption of NoCs. In particular, we make the key observation that even in high load traffic, a number of virtual channels are idle, imposing significant static power overhead. Prior works use power-gating technique to switch off idle VCs and reduce the static power consumption. However, we observe that prior works are mostly suitable for low traffic loads and are ineffective in high traffic loads. In this chapter, we aim to propose a... 

Most of previous studies have assessed the performance issues for regular buffer and virtual channel organiza-tions and have not considered overall buffer size constraint. In this paper, the performance of mesh-based interconnection networks (mesh, torus and hypercube networks) under different traffic patterns (uniform, hotspot, and matrix-transpose) is studied. We investigate the effect of the number of virtual channels and their buffer lengths, on the performance of these topologies when the total buffer size associated to each physical channel (and thus router buffer size) is fixed.The results show that the optimal number of virtual channels and buffer length highly depends on the traffic... 

In this paper, the performance of some popular direct interconnection networks, namely the mesh, torus and hypercube, are studied with adaptive wormhole routing for different traffic patterns. We investigate the effect of the number of virtual channels and depth of their buffers on the performance of such strictly orthogonal topologies under uniform, hot-spot and matrix-transpose traffic patterns for generated messages, while the total buffer size associated to each physical channel is kept constant. In addition we analyze the effect of escape channel buffer length on the performance of a fully adaptive routing algorithm. It is shown that the optimal number of virtual channels and buffer... 

K-ary n-cubes have been one of the most popular interconnection networks for practical multicomputers due to their ease of implementation and ability to exploit communication locality found in many parallel applications. This paper describes an analytical model for k-ary n-cubes with dimension-ordered routing. The main feature of the model is its ability to captures network performance when an arbitrary number of virtual channels are used to reduce message blocking. Simulation experiments reveal that the latency results predicted by the analytical model are in good agreement with those provided by the simulation model. © 2002 Elsevier Science B.V. All rights reserved  

Although several analytical models have been proposed in the literature for binary n-cubes with deterministic routing, most of them have not included the effects of virtual channel multiplexing on network performance. The only mathematical model for deterministic wormhole routing in hypercubes with virtual channels was proposed in [Y. Boura, Design and Analysis of Routing Schemes and Routers for Wormhole-routed Mesh Architectures, Ph.D. Thesis, Department of Computer Science and Engineering, Pennsylvania State University, 1995] which uses complex combinatorial analysis with a computation time of O(N = 2n) for an n-dimensional hypercube. This paper proposes a new and simple analytical model... 

Network-on-Chips (NoCs) employ several virtual channels per input port to mitigate head-of-line blocking issue in transmitting network packets. Unfortunately, these virtual channels are power-hungry resources that significantly contribute to the total power consumption of NoCs. In particular, we make the key observation that even in high load traffic, a number of virtual channels are idle, imposing significant static power overhead. Prior works use power-gating technique to switch off idle VCs and reduce the static power consumption. However, we observe that prior works are mostly suitable for low traffic loads and are ineffective in high traffic loads. In this chapter, we aim to propose a...