Sharif Digital Repository

We propose a partially adaptive fault-tolerant and deadlock-free routing algorithm in n-dimensional meshes based on the fault-tolerant planar-adaptive routing and Duato's protocol. In particular, we show that only four virtual channels per physical channel are sufficient for tolerating multiple faulty regions even in the case of n-dimensional meshes. Our scheme is able to handle faulty blocks whose associated fault rings have overlaps. In addition, it can be used to route messages when fault regions touch the boundaries of the mesh. A flag bit is introduced for guiding misrouted messages. Messages are routed adaptively in healthy regions of the network. Once a message faces a faulty region,... 

The planar-adaptive routing algorithm is a simple method to enhance wormhole routing algorithms for fault-tolerance in meshes but it cannot handle faults on the boundaries of mesh without excessive loss of performance. In this paper, we show that this algorithm can further be improved using a flag bit introduced for guiding misrouted messages. So, the proposed algorithm can be used to route messages when fault regions touch the boundaries of the mesh. We also show that our scheme does not lead to diminish the performance of the network and only three virtual channels per physical channels are sufficient for tolerating multiple boundary faulty regions. © 2008 Springer-Verlag Berlin Heidelberg... 

Many fully-adaptive algorithms have been proposed to overcome the performance limitations of deterministic routing in networks used in high-performance multicomputers, such as the well-known regular n-D torus. This paper proposes a simple yet reasonably accurate analytical performance model to predict message communication latency in tori networks. This model requires a running time of O(1) which is the fastest model yet reported in the literature. Extensive simulations reveal that the new performance model maintains a reasonable accuracy when the network operates under different traffic conditions. The model is then used to perform an extensive investigation into the performance merits of... 

K-ary n-cubes have been one of the most popular interconnection networks for practical multicomputers due to their ease of implementation and ability to exploit communication locality found in many parallel applications. This paper describes an analytical model for k-ary n-cubes with dimension-ordered routing. The main feature of the model is its ability to captures network performance when an arbitrary number of virtual channels are used to reduce message blocking. Simulation experiments reveal that the latency results predicted by the analytical model are in good agreement with those provided by the simulation model. © 2002 Elsevier Science B.V. All rights reserved  

Although several analytical models have been proposed in the literature for binary n-cubes with deterministic routing, most of them have not included the effects of virtual channel multiplexing on network performance. The only mathematical model for deterministic wormhole routing in hypercubes with virtual channels was proposed in [Y. Boura, Design and Analysis of Routing Schemes and Routers for Wormhole-routed Mesh Architectures, Ph.D. Thesis, Department of Computer Science and Engineering, Pennsylvania State University, 1995] which uses complex combinatorial analysis with a computation time of O(N = 2n) for an n-dimensional hypercube. This paper proposes a new and simple analytical model... 

Network-on-Chips (NoCs) usually use regular mesh-based topologies.Regular mesh topologies are not always efficient because of power and area constraints which should be considered in designing system-on-chips.To overcome this problem,irregular mesh NoCs are used for which the design of routing algorithms is an important issue.This paper presents a novel routing algorithm for irregular mesh-based NoCs called "i-route". In contrast to other routing algorithms,this algorithm can be implemented on any arbitrary irregular mesh NoC without any change in the place of IPs. In this algorithm, messages are routed using only 2 classes of virtual channels. Simulation results show that using only 2... 

Network-on-Chips (NoCs) employ several virtual channels per input port to mitigate head-of-line blocking issue in transmitting network packets. Unfortunately, these virtual channels are power-hungry resources that significantly contribute to the total power consumption of NoCs. In particular, we make the key observation that even in high load traffic, a number of virtual channels are idle, imposing significant static power overhead. Prior works use power-gating technique to switch off idle VCs and reduce the static power consumption. However, we observe that prior works are mostly suitable for low traffic loads and are ineffective in high traffic loads. In this chapter, we aim to propose a... 

Network-on-Chips (NoCs) employ several virtual channels per input port to mitigate head-of-line blocking issue in transmitting network packets. Unfortunately, these virtual channels are power-hungry resources that significantly contribute to the total power consumption of NoCs. In particular, we make the key observation that even in high load traffic, a number of virtual channels are idle, imposing significant static power overhead. Prior works use power-gating technique to switch off idle VCs and reduce the static power consumption. However, we observe that prior works are mostly suitable for low traffic loads and are ineffective in high traffic loads. In this chapter, we aim to propose a... 

Most of previous studies have assessed the performance issues for regular buffer and virtual channel organiza-tions and have not considered overall buffer size constraint. In this paper, the performance of mesh-based interconnection networks (mesh, torus and hypercube networks) under different traffic patterns (uniform, hotspot, and matrix-transpose) is studied. We investigate the effect of the number of virtual channels and their buffer lengths, on the performance of these topologies when the total buffer size associated to each physical channel (and thus router buffer size) is fixed.The results show that the optimal number of virtual channels and buffer length highly depends on the traffic... 

In this paper, the performance of some popular direct interconnection networks, namely the mesh, torus and hypercube, are studied with adaptive wormhole routing for different traffic patterns. We investigate the effect of the number of virtual channels and depth of their buffers on the performance of such strictly orthogonal topologies under uniform, hot-spot and matrix-transpose traffic patterns for generated messages, while the total buffer size associated to each physical channel is kept constant. In addition we analyze the effect of escape channel buffer length on the performance of a fully adaptive routing algorithm. It is shown that the optimal number of virtual channels and buffer... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation... 

High reliability, high performance, low power consumption are the main objectives in the design of NoCs. These three design objectives are mostly conflicting and should be considered simultaneously in order to have an optimal design. This paper proposes a method based on duplicating the virtual channels of each NoC node as well as parity codes to prevent SEUs from producing erroneous data. The method is compared with two widely used SEU-tolerant methods i.e., the Switch to Switch and the End to End flow control methods, in terms of reliability, power consumption and performance. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results.... 

A method to setup virtual point-to-point links between the cores of a packet-switched network-on-chip is presented in this paper which aims at reducing the NoC power consumption and delay. The router architecture proposed in this paper provides packet-switching, as well as a number of virtual point-to-point, or VIP (VIrtual Point-to-point) for short, connections. This is achieved by designating one virtual channel at each physical channel of a router to bypass the router pipeline. The mapping and routing algorithm exploits these virtual channels and tries to virtually connect the source and destination nodes of high-volume communication flows during task-graph mapping and route selection... 

Network-on-Chip (NoC) is a precious approach to handle huge number of transistors by virtue of technology scaling to lower than 50nm. Virtual channels have been introduced in order to improve the performance according to a timing multiplexing concept in each physical channel. The incremental effect of virtual channels on power consumption has been shown in literatures. The issue of power saving has always been controversial to many designers. In this paper, we introduce a new technique which tries to adaptively mange the number of virtual channels in order to reduce the power consumption while not degrading the performance of the network without any reconfiguration. Our experimental results... 

Power-gating is a promising method for reducing the leakage power of digital systems. In this paper, we propose a novel power-gating scheme for virtual channels in on-chip networks that uses an adaptive method to dynamically adjust the number of active VCs based on the on-chip traffic characteristics. Since virtual channels are used to provide higher throughput under high traffic loads, our method sets the number of virtual channel at each port selectively based on the workload demand, thereby do not negatively affect performance. Evaluation results show that by using this scheme, about 40% average reduction in static power consumption can be achieved with negligible performance overhead  

Many theoretical-based comparison studies, relying on graph structural and algorithmic properties, have been conducted for the hypercube and the star graph. None of these studies, however, have considered real working conditions and implementation limits. We have compared the performance of the star and hypercube networks for different message lengths and number of virtual channels, and considered two implementation constraints, namely the constant bisection bandwidth and constant node pin-out. We use two accurate analytical models, already proposed for the star graph and hypercube, and implement the parameter changes imposed by technological implementation constraints. When no constraint is... 

Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Thus, it is of crucial importance for a designer to ha ve access to fast methods for evaluating the performance of on-chip networks. To this end, we present a Markovian model for evaluating the latency and energy consumption of on-chip networks. We compute the a verage delay due to path contention, virtual channel and crossbar switch arbitration using a queuing-based approach, which can capture the blocking phenomena of wormhole switching quite accurately. The model is then used to estimate the power consumption of all routers in NoCs. The performance...