Sharif Digital Repository

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and point-to-point interconnects), throughput, and reliability are among the most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular and reusable structures with regularity of structural pattern. However, since NoCs are resource-limited, determining how to distribute application load over limited on-chip resources (e.g. switches, buffers, virtual channels, and wires) in order to improve the metrics of interest and satisfy... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs. Such networks have shorter communication hop count, compared to 2D NoCs, and enjoy fast and power efficient TSV wires in vertical links. Unfortunately, the fabrication process of TSV connections has not matured yet, which results in poor vertical links yield. In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links. AFRA is designed to be simple, high performance, and robust. The simplicity is achieved by applying ZXY and XZXY routings in the absence and presence of fault, respectively.... 

Power-gating is a promising method for reducing the leakage power of digital systems. In this paper, we propose a novel power-gating scheme for virtual channels in on-chip networks that uses an adaptive method to dynamically adjust the number of active VCs based on the on-chip traffic characteristics. Since virtual channels are used to provide higher throughput under high traffic loads, our method sets the number of virtual channel at each port selectively based on the workload demand, thereby do not negatively affect performance. Evaluation results show that by using this scheme, about 40% average reduction in static power consumption can be achieved with negligible performance overhead  

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation... 

Many theoretical-based comparison studies, relying on graph structural and algorithmic properties, have been conducted for the hypercube and the star graph. None of these studies, however, have considered real working conditions and implementation limits. We have compared the performance of the star and hypercube networks for different message lengths and number of virtual channels, and considered two implementation constraints, namely the constant bisection bandwidth and constant node pin-out. We use two accurate analytical models, already proposed for the star graph and hypercube, and implement the parameter changes imposed by technological implementation constraints. When no constraint is... 

Network-on-Chip (NoC) is a precious approach to handle huge number of transistors by virtue of technology scaling to lower than 50nm. Virtual channels have been introduced in order to improve the performance according to a timing multiplexing concept in each physical channel. The incremental effect of virtual channels on power consumption has been shown in literatures. The issue of power saving has always been controversial to many designers. In this paper, we introduce a new technique which tries to adaptively mange the number of virtual channels in order to reduce the power consumption while not degrading the performance of the network without any reconfiguration. Our experimental results... 

A method to setup virtual point-to-point links between the cores of a packet-switched network-on-chip is presented in this paper which aims at reducing the NoC power consumption and delay. The router architecture proposed in this paper provides packet-switching, as well as a number of virtual point-to-point, or VIP (VIrtual Point-to-point) for short, connections. This is achieved by designating one virtual channel at each physical channel of a router to bypass the router pipeline. The mapping and routing algorithm exploits these virtual channels and tries to virtually connect the source and destination nodes of high-volume communication flows during task-graph mapping and route selection... 

Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results. ©2008 IEEE  

Network-on-Chips (NoCs) usually use regular mesh-based topologies.Regular mesh topologies are not always efficient because of power and area constraints which should be considered in designing system-on-chips.To overcome this problem,irregular mesh NoCs are used for which the design of routing algorithms is an important issue.This paper presents a novel routing algorithm for irregular mesh-based NoCs called "i-route". In contrast to other routing algorithms,this algorithm can be implemented on any arbitrary irregular mesh NoC without any change in the place of IPs. In this algorithm, messages are routed using only 2 classes of virtual channels. Simulation results show that using only 2... 

Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Thus, it is of crucial importance for a designer to ha ve access to fast methods for evaluating the performance of on-chip networks. To this end, we present a Markovian model for evaluating the latency and energy consumption of on-chip networks. We compute the a verage delay due to path contention, virtual channel and crossbar switch arbitration using a queuing-based approach, which can capture the blocking phenomena of wormhole switching quite accurately. The model is then used to estimate the power consumption of all routers in NoCs. The performance... 

We propose a partially adaptive fault-tolerant and deadlock-free routing algorithm in n-dimensional meshes based on the fault-tolerant planar-adaptive routing and Duato's protocol. In particular, we show that only four virtual channels per physical channel are sufficient for tolerating multiple faulty regions even in the case of n-dimensional meshes. Our scheme is able to handle faulty blocks whose associated fault rings have overlaps. In addition, it can be used to route messages when fault regions touch the boundaries of the mesh. A flag bit is introduced for guiding misrouted messages. Messages are routed adaptively in healthy regions of the network. Once a message faces a faulty region,... 

The planar-adaptive routing algorithm is a simple method to enhance wormhole routing algorithms for fault-tolerance in meshes but it cannot handle faults on the boundaries of mesh without excessive loss of performance. In this paper, we show that this algorithm can further be improved using a flag bit introduced for guiding misrouted messages. So, the proposed algorithm can be used to route messages when fault regions touch the boundaries of the mesh. We also show that our scheme does not lead to diminish the performance of the network and only three virtual channels per physical channels are sufficient for tolerating multiple boundary faulty regions. © 2008 Springer-Verlag Berlin Heidelberg... 

High reliability, high performance, low power consumption are the main objectives in the design of NoCs. These three design objectives are mostly conflicting and should be considered simultaneously in order to have an optimal design. This paper proposes a method based on duplicating the virtual channels of each NoC node as well as parity codes to prevent SEUs from producing erroneous data. The method is compared with two widely used SEU-tolerant methods i.e., the Switch to Switch and the End to End flow control methods, in terms of reliability, power consumption and performance. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results.... 

Interconnect networks employing wormhole-switching play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs, Multicomputer systems and System Area Networks. Virtual channels greatly improve the performance of wormhole-switched networks because they reduce blocking by acting as "bypass" lanes for non-blocked messages. Capturing the effects of virtual channel multiplexing has always been a crucial issue for any analytical model proposed for wormhole-switched networks. Dally [8] has developed a model to investigate the behaviour of this multiplexing which have been widely employed in the subsequent analytical models of most routing algorithms suggested in the...