Sharif Digital Repository

Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

With progress in integrated circuits technology, on chip systems have become operational, and after that, onchip network are as solutions to improve onchip connections and also its scalability. With improving technology, the number of cores on chips can be more, that it causes increasing importance of produced problems by parallel links. Serial links are one of the methods to decrease these problems. Serial links have some advantages in compare with parallel links in some aspects like: clock pulse skew, cross talk, area cost, difficulties in wiring and synchronizing clock pulse signals. But any way, problems such as high operational frequency and complicated serializer and deserializer... 

Recent advances in VLSI technology have led to integrate a few billion transistors on a chip. Systems on Chip provide solutions to the design problems of these systems. As technology scales down to deep sub-micron dimensions, the delay and power consumption of global interconnects become the major bottleneck in SoC design. Networks on Chip (NoCs) have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in large VLSI design. The market trend to mobile digital systems and battery-powered devices add power as a new dimension to VLSI design space in addition to speed and area. Interconnect wires dissipate a significant fraction of power... 

Today, data analysis has become a valuable tool in various fields in order to discover the forms or abnormal behavior of the system. For example, detecting credit card fraud, network intrusion, or detecting defects in sensors. In this thesis, a method for fault analysis is presented, which can be used as a monitoring tool to monitor the data that is received in a time series from an Internet of Things system and understand the behavior of the system. This method is designed in such a way that by matching the components with the input data, in general, it is applicable for our desired time series. The presented algorithm is implemented in an unsupervised environment using a statistical... 

Deep learning, as a subdivision of machine learning, attempts to model high-level concepts by using a deep graph, consisting of several layers of linear and nonlinear transformations. Implementing these algorithms on hardware is a big challenge.¬This project offers a system in which various hardware methodologies can be used to implement deep learning algorithms side by side. The overall structure of the system consists of high-level programming interfaces for implementation and expression of machine learning algorithms by the user, which will be available as libraries in a high-level programming language such as Python, Ruby, and Julia. These interfaces allow the user to evaluate their... 

This research presents, for the first time, the low-energy checkpointing technique to guarantee the reliability of multiple preemptive periodic mixed-criticality tasks in a multicore platform. In our first research, the number of tolerable faults for each execution section of a task is determined through proposed formulas to meet the reliability target based on safety standards. Then, our proposed method determines the number of checkpoints and their non-uniform intervals for the normal and overrun sections of each task to reduce energy consumption, respectively. Moreover, the unified demand bound function (DBF) analysis is proposed for analyzing the schedulability of the task set.... 

Three dimensional or vertical integration is a new way of increasing the performance and expanding the capacities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. 3D Networks on chip have a lot of benefits such as capability of large scale integration, increasing the density of elements on chip and expanding the dimensions of chips. Large scale integration and increasing density of elements will cause more consumption of energy. This more energy consumption will cause high temperature in chips. Although high temperature has been managed in 2D networks, but necessity of... 

Non-deterministic finite automata (NFA) are an elementary type of Turing machines with very high processing power. NFA processors provide parallelism at the data and task level because they can be in several different output states in one clock cycle. Implementing such machines with memory is a good strategy because if we consider each of the memory columns as a state, by selecting a row of the memory, we can activate several states at the same time, which is an implementation of NFA. NFA-based automata processors were first introduced by Micron and were very powerful for issues such as pattern matching, DNA sequencing, or regular expressions and, in general, for machine learning topics.... 

With increasing number of processors on a chip, the role of interconnections becomes more important in both power consumption and bandwidth. As a result, in MultiProcessor System-on-Chip architectures, the design constraints will shift from "Computational Constraints" to "Communicational Constraints". Nowadays, optical information transfer is introduced as a suitable substitution for electrical interconnections in chips, which can eliminate their problems. Many different optical networks have been presented so far. These networks can be divided into two subcategories. Networks of the first category use an electrical infrastructure as well as optical one. Hence, the scalability of scheme is... 

The increasing complexity of embedded systems has led to the integration of tasks with various degrees of criticality on a common hardware platform called a mixed-criticality system. These systems typically exploit the inherent redundancy of multicore systems to employ the fault-tolerant techniques to satisfy the required target reliability. On the other hand, the use of fault-tolerant techniques increases the time that cores are simultaneously active with maximum power, which can violate the thermal design power (TDP) and exceed the safe temperature of the chip. This activates the dynamic thermal manage- ment (DTM) technique. Some of the most well-known methods to reduce the chip surface... 

Combination of 3D IC technology and network on chip (NoC) is an effective solution to increase system scalability, and also alleviate the interconnect problem in large scale integrated circuits. However, due to the increased power density in 3D NoC systems and the destructive impact of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. Since hardware thermal control techniques, such as DVFS, can cause significant degradation on chip performance, in this thesis we propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in 3D NoCs. The objective of this... 

Three dimensional or vertical integration is a new way of increasing the performance and expanding the capabilities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. Using the third dimension, different topologies could be implemented in these chips and positive effects of this integration like decreasing the length of interconnections and decreasing the communication latency as the result of that could be utilized. In addition to common topologies like mesh and torus, it is possible to implement other structures in three dimensional integration. Topologies with lower... 

Integrating hundreds of cores on a single chip necessitates high performance interconnection network. Due to great delay and power consumption of electrical networks in global connections, their use might be limited in future. Optical networks-on-chip are introduced recently as a proper alternative for electrical networks by providing high bandwidth, low latency, and low power consumption. Despite these outstanding advantages, optical component behavior is very sensitive to temperature fluctuations. Specifically, thermal variations affect refractive index of semiconductor, which in turn change resonating wavelength of micro-ring resonator. Therefore, the switch cannot operate properly and... 

The number of transistors on a single chip is growing exponentially which results in a huge increase in consumed power and temperature. Parallel processing is a solution which concentrates on increasing the number of cores instead of improving single thread performance. Graphics Processing Units (GPUs) are parallel accelerators which are categorized as manycore systems. However, recent research shows that their consumed power and energy are increasing. In this research, we aim to propose methods to make GPGPUs energy effiecient. In this regard, we evaluated the detailed consummed power of GPGPUs. Our results show that memory sub-system is a critical bottelneck in terms of performance and... 

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though... 

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with... 

Recently, a new tool in the study of two-dimensional continuous phase transition was provided by Schramm-Loewner evolution. The main part of SLE is a conformal map which relates growth process of a two-dimensional simple curve to one-dimensional motion on the real axis (so-called Loewner driving function). Time evolution of this map and Loewner driving function is connected via the Loewner differential equation. It turns out that for a certain class of stochastic and conformally invariant curves in two dimensions, the driving function shows Brownian motion in one dimension. Strength point of SLE comes from this fact that all the geometrical properties of such curves is described through a... 

Schramm Loewner evolution (SLE) is a one-parameter family of random simple curves in the complex plane introduced by Schramm in 1999 which is believed to describe the scaling limit of a variety of domain interfaces at criticality. This thesis is concerned with statistical properties of watersheds dividing drainage basins. The fractal dimension of this model is 1.22 which is consistent with the known fractal dimension for several important models such as Invasion percolation and minimum spanning trees (MST). We present numerical evidences that in the scaling limit this model are SLE curves with =1.73, being the only known physical example of an
SLE with <2. This lies outside the... 

As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the...