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Design and Evaluation of a 3D Network on chip with an Efficient Topology

Mehdizadeh Amiraski, Maziar | 2010

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 40961 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shahin
  7. Abstract:
  8. Three dimensional or vertical integration is a new way of increasing the performance and expanding the capabilities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. Using the third dimension, different topologies could be implemented in these chips and positive effects of this integration like decreasing the length of interconnections and decreasing the communication latency as the result of that could be utilized. In addition to common topologies like mesh and torus, it is possible to implement other structures in three dimensional integration. Topologies with lower diameter like tree are a group of these structures which have lower hop counts. But we know that these topologies have their own problems. In this thesis we try to evaluate the mesh of trees topology, which is an effort to combine the positive characteristics of mesh and tree topologies, under 3D implementation and to determine its strengths and costs. As we will see, utilizing the third dimension in this network and decreasing the size of interconnects would decrease the network’s total power consumption, its packet latency, and power-delay product as their result.


  9. Keywords:
  10. Network-on-Chip (NOC) ; Three Dimensional Integration ; Mesh Tree Network ; Vertical Interconnects

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