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patooghy--ahmad
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Soft Error & Crosstalk Fault Mitigation in Network-On-Chips
, Ph.D. Dissertation Sharif University of Technology ; Miremadi, Ghassem (Supervisor)
Abstract
Recent advances in VLSI technologies have enabled current silicon dies to accommodate billions of transistors in the design of very complex System-on-Chips (SoCs). To address the resulting complexity, Network-on-Chips (NoCs) have emerged as a paradigm to design scalable communication architecture to connect the processing cores of an SoC. However, smaller feature sizes, lower voltage levels and higher frequencies in Deep Sub-Micron (DSM) technologies make NoCs highly susceptible to transient faults, e.g., crosstalks, particle strikes, electro-magnetic interferences, and power supply disturbances. Single Event Upsets (SEUs) caused by high energy particle strikes as well as crosstalks are the...
XYX: a power & performance efficient fault-tolerant routing algorithm for network on chip
, Article Proceedings of the 17th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2009, 18 February 2009 through 20 February 2009, Weimar ; 2009 , Pages 245-251 ; 9780769535449 (ISBN) ; Miremadi, G ; Sharif University of Technology
2009
Abstract
Reliability is one of the main concerns in the design of network on chips due to the use of deep-sub micron technologies in fabrication of such products. This paper proposes a fault-tolerant routing algorithm called XYX which is based on sending redundant packets through the paths with lower traffic loads. The XYX routing algorithm makes a redundant copy of each packet at the source node and exploits two different routing algorithms to route the original and the redundant packets. Since two copies of each packet reach the destination node, the erroneous packet is detected and replaced with the correct one. Due to the use of paths with lower traffic rates for sending redundant packets and...
Complement routing: A methodology to design reliable routing algorithm for network on chips
, Article Microprocessors and Microsystems ; Volume 34, Issue 6 , 2010 , Pages 163-173 ; 01419331 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2010
Abstract
Use of deep sub-micron VLSI technologies in fabrication of Network on Chips (NoCs) makes the reliability to be one of the first order concerns in the design of these products. This paper proposes and evaluates a methodology that adds reliability to NoC routing algorithms with minimal power and performance overheads. The key idea behind this methodology is to use the concept of complement routing in which two routing algorithms with disjoint sets of allowed turns are incorporated. According to this methodology, while a packet is routed by a routing algorithm, a redundant copy of that packet is routed by the complement of that routing algorithm. This is done by exploiting channels with lower...
Comparative analytical performance evaluation of adaptivity in wormhole-switched hypercubes
, Article Simulation Modelling Practice and Theory ; Volume 15, Issue 4 , 2007 , Pages 400-415 ; 1569190X (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
2007
Abstract
In this paper, we study the effect of adaptivity of the routing algorithm on the overall performance of a hypercube multicomputer using wormhole switching. To this end, we use three accurate analytical models proposed for deterministic, fully-adaptive, and partially-adaptive routing algorithms in the hypercube. We compare these three different classes of routing algorithms under different working conditions and structural factors. It is widely believed that the level of adaptivity can result in better performance. Our analysis shows that under uniform traffic load, the employed partially-adaptive routing algorithm exhibits a lower performance compared to the considered deterministic routing...
Analytical performance modelling of partially adaptive routing in wormhole hypercubes
, Article 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006, 25 April 2006 through 29 April 2006 ; Volume 2006 , 2006 ; 1424400546 (ISBN); 9781424400546 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
IEEE Computer Society
2006
Abstract
Although several analytical models have been proposed in the literature for different interconnection networks with different routing algorithms, there is only one work dealing with partially adaptive routing algorithms. This paper proposes an accurate analytical model to predict message latency in wormhole-routed hypercube based networks using the partially adaptive routing algorithm. The results obtained from simulation experiments confirm that the proposed model exhibits a good accuracy for various network sizes and under different operating conditions. © 2006 IEEE
An accurate mathematical performance model of partially adaptive routing in binary n-cube multiprocessors
, Article Mathematical and Computer Modelling ; Volume 48, Issue 1-2 , 2008 , Pages 34-45 ; 08957177 (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
2008
Abstract
Although several analytical models have been proposed in the literature for different interconnection networks with different routing algorithms, there is only one work [M. Ould-Khaoua, An approximate performance model for partially adaptive routing algorithm in hypercubes, Microprocessors and Microsystems 23 (1999) 185-190] dealing with partially adaptive routing. It is not accurate enough especially in heavy traffic regions due to the rough approximation of assuming equal traffic rate over network channels. We show, however, such an approximation can greatly affect the accuracy of the model. This paper proposes an accurate analytical model to predict the average message latency in wormhole...
LTR: A low-overhead and reliable routing for network on chips
, Article 2008 International SoC Design Conference, ISOCC 2008, Busan, 24 November 2008 through 25 November 2008 ; Volume 1 , Volume 1 , 2008 , Pages 129-133 ; 9781424425990 (ISBN) ; Miremadi, S. G ; Sharif University of Technology
IEEE Computer Society
2008
Abstract
A fault tolerant routing algorithm is presented in this paper. proposed routing algorithm is based on making a redundant of each packet as well as sending the redundant packets the paths with low traffic loads. Since two copies of each reach the destination node, the erroneous packets are and replaced with the correct ones. To effectively use paths with lower traffic loads, the redundant packets are according to YX routing while the original packets are according to Duato's routing algorithm. Minimizing the of sent redundant packets and exploiting different paths sending the original and redundant packets enable the algorithm to improve the reliability of NoCs with power and performance...
Analytical performance comparison of deterministic, partially- And fully-adaptive routing algorithms in binary n-cubes
, Article 12th International Conference on Parallel and Distributed Systems, ICPADS 2006, Minneapolis, MN, 12 July 2006 through 15 July 2006 ; Volume 2 , 2006 , Pages 21-28 ; 15219097 (ISSN); 0769526128 (ISBN); 9780769526126 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
2006
Abstract
In this paper, we study the effect of adaptivity of routing algorithm on the overall performance in a hypercube multicomputer using wormhole switching. To this end, we use three accurate analytical models proposed for deterministic, fully-adaptive, and partially-adaptive routing algorithms in hypercube. Surprisingly, our analysis shows that under uniform traffic load, the partially-adaptive routing exhibits a lower performance compared to the deterministic routing with less adaptivity. ©2006 IEEE
Performance comparison of partially adaptive routing algorithms
, Article 20th International Conference on Advanced Information Networking and Applications, Vienna, 18 April 2006 through 20 April 2006 ; Volume 2 , 2006 , Pages 763-767 ; 1550445X (ISSN) ; 0769524664 (ISBN); 9780769524665 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
2006
Abstract
Partially adaptive routing algorithms are a useful category of routing algorithms due to their simple router logic and restricted adaptivity in selecting the next output channel towards the destination. Several partially adaptive routing algorithms on mesh and hypercube networks have been presented in the literature. But there is no study on evaluating the performance of these algorithms. This paper tries to compare the most important partially adaptive routing algorithms on the mesh and hypercube networks as the most popular topologies for multicomputers. The evaluation has been performed by the use of event driven simulator coded by C++ compiler. © 2006 IEEE
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
, Article Microprocessors and Microsystems ; Volume 35, Issue 8 , 2011 , Pages 766-778 ; 01419331 (ISSN) ; Miremadi, S. G ; Tabkhi, H ; Sharif University of Technology
2011
Abstract
This paper proposes a power-efficient flow-control method to tackle the problem of crosstalk faults in Network-on-Chips (NoCs). The method, called FRR (Flit Reordering/Rotation), combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a flit sequence which produces the lowest number of OD transitions on NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of...
An efficient method to reliable data transmission in Network-on-Chips
, Article Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, 1 September 2010 through 3 September 2010, Lille ; 2010 , Pages 467-474 ; 9780769541716 (ISBN) ; Tabkhi, H ; Miremadi, S. G ; Sharif University of Technology
2010
Abstract
Data transmission in Network-on-Chips (NoCs) is a serious problem due to crosstalk faults happening in adjacent communication links. This paper proposes an efficient flow-control method to enhance the reliability of packet transmission in Network-on-Chips. The method investigates the opposite direction transitions appearing between flits of a packet to reorder the flits in the packet. Flits are reordered in a fixed-size window to reduce: 1) the probability of crosstalk occurrence, and 2) the total power consumed for packet delivery. The proposed flow-control method is evaluated by a VHDL-based simulator under different window sizes and various channel widths. Simulation results enable NoC...
Crosstalk modeling to predict channel delay in Network-on-Chips
, Article Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 3 October 2010 through 6 October 2010 ; October , 2010 , Pages 396-401 ; 10636404 (ISSN) ; 9781424489350 (ISBN) ; Miremadi, S. G ; Shafaei, M ; Sharif University of Technology
2010
Abstract
Communication channels in Network-on-Chips (NoCs) are highly susceptible to crosstalk faults due to the use of nano-scale VLSI technologies in the fabrication of NoCs. Crosstalk faults cause variable timing delay in NoC channels based on the patterns of transitions appearing on the channels. This paper proposes an analytical model to estimate the timing delay of an NoC channel in the presence of crosstalk faults. The model calculates expected number of 4C, 3C, 2C, and 1C transition patterns to predict delay of a K-bit communication channel. The model is applicable for both non-protected channels and channels which are protected by crosstalk mitigation methods. Spice simulations are done in a...
A low-overhead and reliable switch architecture for Network-on-Chips
, Article Integration, the VLSI Journal ; Volume 43, Issue 3 , June , 2010 , Pages 268-278 ; 01679260 (ISSN) ; Miremadi, S. G ; Fazeli, M ; Sharif University of Technology
2010
Abstract
This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation...
Analytic modeling of channel traffic in n-cubes
, Article 1st International Computer Science Symposium in Russia, CSR 2006, St. Petersburg, 8 June 2006 through 12 June 2006 ; Volume 3967 LNCS , 2006 , Pages 567-579 ; 03029743 (ISSN) ; Mahini, H ; Patooghy, A ; Sharif University of Technology
Springer Verlag
2006
Abstract
Many studies have shown that the imbalance of network channel traffic is of critical effect on the overall performance of multicomputer systems. In this paper, we analytically model the traffic rate crossing the network channels of a hypercube network under different working conditions. The effect of different parameters on the shaping of non-uniformity and traffic imbalance over network channels, are considered and analytical models for each case are proposed. © Springer-Verlag Berlin Heidelberg 2006
Reducing power consumption in NoC design with no effect on performance and reliability
, Article 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, 11 December 2007 through 14 December 2007 ; 2007 , Pages 886-889 ; 1424413788 (ISBN); 9781424413782 (ISBN) ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
2007
Abstract
High reliability, low power consumption and high performance are key objectives in the design of NoCs. These three design objectives should be considered simultaneously in order to have an optimal design. This paper proposes a method to reduce power consumption of an application specific NoC. This is done in two steps: 1) Extra virtual channels are used in the router architecture to increase the performance in an application specific NoC, and 2) The amount of the performance gain is then set to the initial point using frequency scaling technique, hence reducing the power consumption, without corruption of reliability. The simulation results show that the method can reduce the power...
A low-power and SEU-tolerant switch architecture for network on chips
, Article 13th Pacific Rim International Symposium on Dependable Computing, PRDC 2007, Melbourne, VIC, 17 December 2007 through 19 December 2007 ; 2007 , Pages 264-267 ; 0769530540 (ISBN) ; 9780769530543 (ISBN) ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
2007
Abstract
High reliability, high performance, low power consumption are the main objectives in the design of NoCs. These three design objectives are mostly conflicting and should be considered simultaneously in order to have an optimal design. This paper proposes a method based on duplicating the virtual channels of each NoC node as well as parity codes to prevent SEUs from producing erroneous data. The method is compared with two widely used SEU-tolerant methods i.e., the Switch to Switch and the End to End flow control methods, in terms of reliability, power consumption and performance. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results....
Performance modelling of necklace hypercubes
, Article 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007 ; 2007 ; 1424409101 (ISBN); 9781424409105 (ISBN) ; Sarbazi Azad, H ; Patooghy, A ; Sharif University of Technology
2007
Abstract
The necklace hypercube has recently been introduced as an attractive alternative to the well-known hypercube. Previous research on this network topology has mainly focused on topological properties, VLSI and algorithmic aspects of this network Several analytical models have been proposed in the literature for different interconnection networks, as the most cost-effective tools to evaluate the performance merits of such systems. This paper proposes an analytical performance model to predict message latency in wormhole-switched necklace hypercube interconnection networks with fully adaptive routing. The analysis focuses on a fully adaptive routing algorithm which has been shown to be the most...
RMAP: A reliability-aware application mapping for network-on-chips
, Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 112-117 ; 9780769540900 (ISBN) ; Tabkhi, H ; Miremadi, S. G ; IARIA ; Sharif University of Technology
2010
Abstract
This paper proposes a reliability-aware application mapping for mesh-based NoCs. The proposed reliable mapping, called RMAP, adds redundant communications to the application graph in order to improve the reliability of packet delivery in NoCs. The RMAP divides the application graph into two sub-graphs which have the lowest possible communication with each other. One of the sub-graphs is mapped on the upper triangular nodes of the NoC and the other is mapped on the lower triangular nodes. In this way, lower traffic load is imposed on some channels which are efficiently used to route packets of redundant communications. This minimizes the overheads imposed to the NoC due to redundant...
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
, Article IET Computers and Digital Techniques ; Volume 3, Issue 3 , 2009 , Pages 289-303 ; 17518601 (ISSN) ; Miremadi, S. G ; Ejlali, A ; Patooghy, A ; Sharif University of Technology
2009
Abstract
Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the...
An efficient technique to tolerate MBU faults in register file of embedded processors
, Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 115-120 ; 9781467314824 (ISBN) ; Fazeli, M ; Patooghy, A ; Miremadi, S. G ; Sharif University of Technology
2012
Abstract
This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file...