Sharif Digital Repository

While digital IC technology scales down, the impact of size effects in copper interconnects become more important because wire dimensions reach the same order of electron mean free path yielding increased resistivity of metal due to surface and grain boundary scatterings. Hence, because of their longer MFP, Carbon nanotubes are proposed as potential candidates for replacing copper interconnects. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid grows in current densities which increases the temperature of IC and interconnects as well. Sub-ambient cooling has long been suggested for improving the performance of... 

Recently, the size of copper interconnects is going to reach lower than the mean free path of electrons for copper. In this situation, we should consider the effect of other scattering mechanisms as well as thermal scattering on copper thin films. In this work we study both DC size effect and anomalous skin effect on resistivity by a Monte Carlo method. Contribution of each scattering mechanism and the interaction between them are analyzed separately. The structure of electrical field and distribution of current in thin films have also been studied. Investigating of the effect of exact nature of surface scattering and grain boundary scattering on resistivity is one of the interests of this... 

In this thesis, the simulation of HEMT for high frequency applications has been explored. It has been tried to examine the changes such as: gate recess, T-shaped gate, changing the channel length and doping of buffer layer on the performance of the proposed device. Simulation results show that the best way to improve the device performance, in particular its cut-off frequency, is increase in buffer layer doping density. Because it significantly increase the saturation current, electron mobility inside the channel, the transconductance and the cut-off frequency. If we need to lower the noise, the T-shaped gate can also be used. Also, by change in doping of donor layer, amount of 1017 cm-3 is... 

The exponential increase in power density within a chip due to higher frequency of operation in recent years (Moor's law) is a major limiting factor for designers. Increasing the number of parallel cores instead of increasing the frequency of operation is a possible solution. The design of connections within the cores can be followed by the old process but the global interconnectsbetween the cores instead of point to point can be replaced byNetwork-on-Chip (NoC). In this thesis, The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of coppe. The optimal... 

Since interconnects are playing a very important role in today’s IC technology, introducing new models and approximations is vital to IC designers. In this dissertation, maxwell equations are introduced as they are the main equations governing transmission lines. Different methods to model interconnects are also presented. Moreover, because of the importance of the step response of a system, available methods for finding the step response of interconnects are briefly discussed. Some approximations are also described, which result in faster but not very accurate responses. Delay and noise in integrated circuit connections have been the subject of several investigations for a long time. Since... 

Due to the growth of information volume and increment in the speed of processor units, it is critical to achieve higher speed in data transaction systems. This necessity could be recognized in all fields, from digital data transactions on a chip and among its building blocks to data transactions among electronic boards and computerized systems in huge control constructions.
Methods of data transmission have been improved both in terms of speed and simplicity for different applications in today’s enormous consumer electronics market. One possible option is to use conventional wires as physical channel of transmission system.
The most important drawback of the wires is their relative... 

Delay of Interconnects in modern digital ICs is several times greater than delay of gates. One proper measure for this problem is to shorten interconnects length by using three dimensional structures instead of conventional two dimensional structures. In these structures TSVs (Through Silicon Vias) make connection between stratums. Power integrity in 3D ICs necessitates power distribution networks to have minimum IR drop and Ldi/dt noise. In this dissertation we design power distribution network considering IR drop and Ldi/dt noise margin. We expand a mathematical model which represents differential equation of power distribution in the surface of each stratum. Using this expanded model we... 

As the transistors’ dimensions in integrated circuits shrink, according to Moore’s law, a number of challenges emerges that can decrease the benefits of scaling. One of the main challenges in deep submicron CMOS technologies is the delay in interconnects. In recent years, researchers have been looking into different methods to minimize the delay in interconnects. International Technology Roadmap for Semiconductors (ITRS) predicts that the input capacitance of a buffer will become in the order of 10s of aFs with technology scaling. This will give us the opportunity to transmit the data in electrical interconnects near the speed of light.In this thesis, a novel buffer is designed in which the... 

Several advantages and problems associated with technology scaling. One of the most important problems facing technology scaling is interconnects. As technology scales down wire delay becomes dominant. Optical interconnects has been subject of many researches for more than two decades to overcome this problem. The key idea behind near speed of light transmission (NSoLT) is that for buffers at the end of ITRS projections input capacitances could be as small as tens of atto Farads. Hence, voltage of the end of global wires could jump at the time of flight.
In this project, a global wire has been divided in to k segments in a way that data can be transferred with the speed close to the... 

Today, the internal connections of the CPUs with a few billion wired transistors in 14 copper layers on the silicon wafer are possible. Recently, power dissipation has slowed the growth rate of clock growth in CPUs, and nowadays sometimes more than 60% power is lost in connections. In this situation, the increase in efficiency has been achieved in accordance with Moore's law with multi-core chips. This theme has made the connections between the cores much more important than before. Usually the information in the network structure on chip (NOC) is transmitted on these connections. Therefore, all three aspects of delay, power dissipation and bit rate are important for communication channels.... 

The process of contracting the chips will lead the increasing of impurity concentration, decreasing the bias voltage and threshold voltage to make stable the electrical field. For using the advantage of lesser dimensions of the total circuit using decreasing bias voltage lead the dimension of the wires to be decrease also. Therefore, once the parasitic effects of wires, the RC delays of wires and the noise of power transmission will enhance obviously. With this contracting by process, electrical resistance of interconnect will enhance also. The reason of this matter is that the area chip will decrease significantly. While the operational frequency increases the effect of inductance should be... 

The Technology scaling and reduction of the size of transistors has led to an increase in the switching speed and, as a result, to an increase in the clock frequency.But in recent years, the continuation of this process of increasing the clock frequency has been almost stopped considering the considerations of power consumption. Previous research has shown that approximately 30-50% of the dynamic power consumed by the microprocessor is wasted in the clock distribution network.Therefore, the design of clock distribution networks is a big challenge for future microprocessors due to the trend of Technology scaling and process variation. In this thesis, we used the emerging technology of... 

Developing to the sub-micron dimentions reduces the size of integrated circuits, so interconnects and a variations in their characteristics has more effects on circuit performance. Worst case study is the most common method in these systems, but in many cases interconnect lines are independent from eachother. Analysis state that worst case is out of the distribution in many cases (with zero possibility) and result in a pessimistic design. Statistical analysis should replace worst case analysis in multi varient systems. In this titile, statistical analysis will be used to investigate performance of interconnects in new technology. Maximum variation in interconnect parameters are considered... 

Although a lot of research has been done on Carbon-based interconnect, there are many important questions unanswered. For example, there is no compact model for the resistance of bundle of CNTs at high frequencies, at which interconnects will be operating due to the scaling. Also there are many studies comparing CNT, GNR, and Cu wires but there is no study to show how much this will impact the design of a chip at today’s Giga Scale Integration. This comprehensive study should include chip performance, power dissipation and total number of metal levels. These two big questions are investigated in this dissertation. In the first part, high frequency behavior of CNT bundles is studied. A... 

Due to the physical limitations of the conventional 2D ICs at Giga-Scale Integration, modern technologies have been emerged. Among them, through silicon via (TSV) - based 3D ICs have been used to continue Moore’s law in the interconnect era. In these systems, dies are stacked at z-direction after wafer thinning. Electrical connections between stacked dies are done by TSVs. One important advantage of 3D integration technology is their ability to stack heterogeneous systems with different technologies on a single chip. This will not only increase interconnect density but also will reduce the delay and power consumption. However, nowadays, fabrication and optimum design of TSVs are still big... 

Structure and morphology of titanium dioxide have an excessive effect on the photovoltaic properties of dye-sensitized solar cells (DSCs). Different approaches have been used to improve the efficiency of these cells. One is using a scattering layer. Studies have been shown that properties of scattering layer such as composition and morphology have great effect on photovoltaic properties of solar cell. In this project, the effect of cubic morphology of TiO2 as a scattering agent in photoanode of DSCs is studied. Titanium dioxide with various morphologies including nanoparticles, solid and hollow cubic structures have been synthesized by solvothermal and hydrothermal methods, respectively. The... 

Due to the high cost of the conventional silicon-based circuits, printed electronic introduced as an ultra-low-cost saving techniques which are widely used in RFID tags, displays, sensors and thin film transistors and so on. Unlike the silicon-based devices, Organic materials are used in printed electronic devices, owing to this these devices can be used on large and flexible substrates like glass and plastic. Also in the printing method, there is no demand for expensive and time-consuming processes such as lithography or sputtering. Only by an ink-jet printer or graved cylinders the different layers of a device can be deposited. Besides these advantages of printed electronics to... 

Over the past five decades, the proliferation of electronic devices and the advent of Internet of Things (IoT) technology have ushered in a profound revolution in integrated circuit technology. In contemporary electronics, digital integrated circuits rely predominantly on CMOS transistors. Among the notable limitations associated with CMOS transistors are their non-zero off-state current and limited sub-threshold slope. In response to these limitations, researchers have ventured into a burgeoning field known as "Beyond CMOS," exploring technologies like Tunnel Junctions, Carbon Nanotube FETs, and more. Additionally, alternative approaches that blend electronic and mechanical principles in... 

In this thesis we study circuit models and their step responses of the Interconnects. First of all, we solve the Maxwell’s equations for lossless line to understand the models deeply and then generalize it for lossy lines. Only with equations that govern the model, one can realize the regions in which his model behaves correctly. After that, the transfer function of a single line with arbitrary load and source impedance is derived, based on lossy segmented model. Knowing this, we introduce different methods of getting the inverse Laplace of transfer function and their pros and cons. Finite pole approximation, Fourier series harmonics, and changing variable are various methods to simplify... 

As technology scales down Integrated Circuits operates at higher frequency and lower dimensions. Interconnects inside these chips operate at gigahertz frequencies and manometer range. As mean free path of electrons become comparable with wire dimensions and skin depth, first one will result in Size Effect and second one will result in Anomalous Skin Effect. In this thesis we are trying to characterize these effects. The MFP of electron for copper at room temperature is about 38nm and therefore neither Size effect nor ASE are measurable at room temperature with our available equipment. Hence, the idea is to measure ASE for copper wires at liquid nitrogen temperature (77K). We showed that ASE...