Sharif Digital Repository

In past decades, we have seen the rise of integration density in chips making it possible to design a whole system on a single chip. The previously designed interconnection architectures for multiprocessors systems cannot directly be applied in on-chip systems (especially when the number of processor elements increases) since they require a different type of a cost-performance trade-off. This is why the interconnection networks of systems-on-chip (SoC) are such a problem. Network-on-chip (NoC) was being proposed as a scalable and reusable communication platform for SoCs, which makes use of the network model to develop efficient on-chip communication infrastructures. The NoC has a layered and... 

Processor cores in embedded applications is one the of important part of System-on-Chip designs. Among the most successful (Reduced Instruction Set Computer) RISC cores are the (Million Instruction Per Second) MIPS processors used in applications such as DVD, automotive, broadband access, networking, etc. In this work we have designed and verified Transaction Level Modeling (TLM) architecture of the MIPS in SystemC TLM2.0. The TLM in SystemC is adopted so that abstract data types can be used for higher (abstract) level modeling and faster simulation design. We implemented the processor such that the instruction and data caches contain all the necessary instructions and data to eliminate... 

Advanced RISC Machines (ARM) are an example of a simple processor used to accomplish simple processing tasks in many applications. They can be found in PDA’s, mp3 players, and other portable electronic devices. ARM processors have small instruction sets and basic processor architecture, and they can be modeled in transaction level by SystemC. SystemC is one of many high level programming languages used to write hardware descriptive codes. We have chosen TLM in SystemC so that abstract data types can be used for higher level modeling and faster simulation. System architects and embedded software developers are accepting transaction level modeling into their design flow because it addresses... 

Due to the development of electronics, technology has entered new levels of integration on a single chip, called the System-on-Chip (SoC) design. Currently a SoC may contain various Intellectual Property (IP) cores with different interface protocols. For typical SoC communication, designers implement numerous standards such as Avalon from Altera and AMBA from ARM. These standards have different topologies with their own properties and are suitable for specific applications, But the challengeable problem is testing interconnects between cores. In testing process, important elements of a bus that should be tested are interconnections between cores (wires), multiplexers, arbiters, decoders, and... 

The advancement of technology in the semiconductor industry and the resulting increase in the number of transistors on a chip has led to an increase in the number of processing cores an increase in the number of processing cores in a system on chip (SoC). A surge in the number of processing cores, makes their communication more and more noteworthy. This communication is established through the network on chip (NoC). One of the main challenges in NoC design is power management, as it constitutes a high percentage of the overall power consumption of the chip. One of the most power-hungry components of NoC is the router. According to our observation, some of the components of the routers are...