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A SystemC Transaction Level Modeling of an ARM Processor

Kouchaki, Mohammad Reza | 2010

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  1. Type of Document: M.Sc. Thesis
  2. Language: English
  3. Document No: 41049 (55)
  4. University: Sharif University of Technology, International Campus, Kish Island
  5. Department: Science and Engineering
  6. Advisor(s): Vosughi Vahdat, Bijan; Ghorshi, Mohammad Ali
  7. Abstract:
  8. Advanced RISC Machines (ARM) are an example of a simple processor used to accomplish simple processing tasks in many applications. They can be found in PDA’s, mp3 players, and other portable electronic devices. ARM processors have small instruction sets and basic processor architecture, and they can be modeled in transaction level by SystemC. SystemC is one of many high level programming languages used to write hardware descriptive codes. We have chosen TLM in SystemC so that abstract data types can be used for higher level modeling and faster simulation. System architects and embedded software developers are accepting transaction level modeling into their design flow because it addresses their need for early architecture exploration. Transaction Level Modeling by a standard language, SystemC, becoming the language to propagate the TLM paradigm. We could see that in recent years, most of the content of SoCs will be pre-designed. This occurs along with a move to platforms in which many elements of architecture are predetermined. The TLM-SystemC approach will allow libraries of system components to be developed and reused for different platforms, thus reducing time-to market without compromising SoC quality. In this project, we are going to model the transaction level (TLM) of an ARM processor using SystemC. So, first we are going to discuss the Transaction Level Modeling, SystemC as a language, architecture of a basic ARM processor, and then design the processor step by step
  9. Keywords:
  10. C Programming Language ; Transactional Level Modeling ; Advanced RISC Machine (ARM) ; System-on-Chip

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