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Evaluation of Performance and Power Consumption of the Task Migration Schemes in the Mesh NoC

Goodarzi, Bahareh | 2009

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 40011 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. With the advance of the semiconductor technology, it has been feasible now to fabricate high performance multiprocessor systems-on-chips, containing tens and in the near future hundreds of processing cores. Meanwhile, the diminished technology feature size and high power consumption limit in using previous communication structures such as shared buses. Networks-on-Chip (NoC) have been introduced to obviate these constraints by providing high modularity, scalability and inherent parallelism. Design of these interconnect structures includes multiple tradeoffs between delays, throughput, energy consumption and silicon area requirements. So far, many mechanisms have been proposed to improve the performance of NoCs. Task migration is one of these methods which has attracted many attention in recent years. Simply stated, task migration is transferring a job, task, or process from the node where it is currently running to a new node and then resuming its execution there. The run-time task migration topic has been studied extensively for multicomputer systems since the beginning of the 1980s which mainly aims to balance the workload across the system. However, very specific NoC properties such as limited amount of communication memory, more sensitivity to implementation complexity, and tight latency and power consumption constraints, brings new challenges in applying the current task-migration mechanisms in NoCs. As a consequence, effectiveness and applicability of traditional transparent migration mechanisms are put in discussion in this context. Beyond traditional objectives, Task migration in NoCs helps the thermal chip management by moving tasks away from hot processing elements. In this thesis, we evaluate the performance and power consumption of task migration schemes in the mesh NoC, which has been previously investigated in multicomputer systems. We incorporate simulation to compare the performance and power consumption of NoCs under different task migration schemes. At last, an efficient method is proposed which improves the latency and power consumption, compared to other schemes.
  9. Keywords:
  10. Network-on-Chip (NOC) ; Power Consumption ; Performance Evaluation ; On-Chip Multiprocessor ; Task Mapping ; Task Migration

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