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Design and Implementation of a CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

Moslehi Bajestan, Masoud | 2010

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 40538 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharif Bakhtiar, Mehrdad
  7. Abstract:
  8. A 1.8-v 1.8-GHz fully integrated CMOS fractional-N frequency synthesizer is designed and tested for UHF RFID readers. The synthesizer employs a dual-loop architecture to realize a monolithic design with more optimal trade-off among phase noise, channel spacing, reference frequency and settling time compared to the conventional integer-N phase-locked-loop architecture. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer’s phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. A 1.8-GHz complementary VCO with noise filter has been used to achieve these tough specifications. Also, since a large KVCO can degrade the PLL phase noise and spur performance severely, the VCO adopts a switched tuning LC tank together with an adaptive frequency calibration (AFC) technique. The 900 MHz differential LO signals are obtained by a divide-by-two circuit. The synthesizer employs a dual-path active loop filter to minimize its chip area. The prototype is fabricated in a standard 0.18-μm CMOS process without any external components. The measured phase noise is -109¬dBc/Hz at 100-kHz offset and -128.5¬dBc/Hz at 1-MHz offset from a 1.82-GHz carrier. The worst case fractional spurs over all the measured channels are about -60¬dBc. The total lock time is measured to be less than 200μs. With a chip area of 1.4×1.64 mm2 (including pads and test circuits), the test chip consumes 20.3mW.

  9. Keywords:
  10. Radio Frequency Identification (RFID) ; Radio Frequency Identification (RFID) Reader ; Frequency Synthesizer ; Fractional-N

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