Load Balancing in Network on-Chip<br/>

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Load Balancing in Network on-Chip

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 40997 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Sarbazi Azad, Hamid
Abstract:
This project presents a routing algorithm to cope with the dynamic traffic pattern of network-on-chip (NoC) architectures aiming to distribute the on-chip traffic evenly across the network. In this algorithm, instead of relying solely on local congestion information, the routes are determined based on the global information about on-chip traffic. This is achieved by employing a light-weight and efficient control network which monitors the on-chip traffic and collects the required information for determining the appropriate path between any pairs of communicating nodes in such a way that the congestion is avoided and the NoC load is balanced. Our experiments show that the proposed method outperforms the conventional deterministic and adaptive routing methods across all SPLASH-II benchmarks, with an 23% average and 45% maximum latency reduction. The proposed routing policy involves negligible logic and modest wiring overhead, compared to a conventional NoC.
Keywords:
Network-on-Chip (NOC) ; Load Balancing ; Gratings ; Delay ; Routing ; Deadlock Free Routing Algorithm

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