Loading...

A High-Performance and Low-Power Reconfigurable Network-on-Chip Architecture

Modarressi, Mehdi | 2010

923 Viewed
  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 41483 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. Network-on-Chip (NoC) is a promising on-chip communication paradigm which targets the scalability and predictability problems of the traditional on-chip mechanisms. However, it has been shown that, in future technologies (especially 22 nm technology), the power consumption of the current NoCs is about 10 times higher than the power budget can be devoted to them. Application-specific optimization is one of the most effective approaches to bridge the exiting gap between the current and the ideal NoC power consumptions. However, almost all existing application-specific customization methods try to customize NoCs for a single application (and based on its traffic pattern). Today’s multi-core SoCs are highly complex chips, and as technology advances, it becomes more cost-effective to integrate several different applications into a single SoC. Moreover, NoC-based chip-multiprocessors (CMPs) are applied to run different applications which may not be known at the synthesis time. As a result, NoC architectures should closely match the traffic characteristics and performance requirements of different applications. As different applications have different functionalities, the inter-core communication characteristics can be very different across the applications. Consequently, the NoC that is designed to run exactly one application does not necessarily meet the design constraints of other applications. The objective of this work is to address this problem by proposing a reconfigurable NoC architecture. This architecture can dynamically change its topology, switching method, and buffer configuration in order to match the traffic pattern of the currently running application. Topology reconfiguration is the most important property of the proposed packet-switched NoC. In this architecture, routers are not connected directly to each other, but rather connected through simple switches, called configuration switches. By changing the configuration of these switches, we can chance the connectivity pattern of the nodes, hence the network topology. We develop an algorithm to customize the topology of the NoC for some applications integrated into the same chip. In addition to application-specific topologies, this NoC can be configured as a global bus or multiple local buses, as well. After finding a topology for each application, the power and performance of the NoC can be further optimized by some low-latency and low-power reconfigurable virtual point-to-point connections. These connections are setup over one virtual channel of each physical channel of packet-switched routers which bypasses the entire router pipeline stages. These connections are constructed between the source and destination nodes of some heavy traffic flows, in order to reduce the average latency and power consumption of the NoC. The number of virtual channels and buffer depth of each virtual channel are other parameters which can be dynamically tuned based on the traffic pattern of the running application. A large number of NoC designs can be found in the literature varying from regular tiled-based to fully customized structures. Fully customized NoCs are designed and optimized for a specific application to give the best performance and power results for that application. On the other hand, in regular NoC architectures, designers can solve usual physical design issues like crosstalk tolerance, timing closure, and wire routing and reuse it in several designs. This reusability alleviates the predictability problem in deep sub-micron technologies and effectively reduces the NoC design effort. Our proposed NoC architecture can be placed between these two extreme points and benefit from both worlds. While this NoC architecture can be designed and optimized like a regular NoC, it can be dynamically configured to a structure that best matches the traffic pattern of each running application. In other words, this architecture realizes application-specific NoCs over a regular architecture with structured components
  9. Keywords:
  10. Network-on-Chip (NOC) ; Reconfiguration ; Topology ; Switchy ; Virtual Point-to-Point Links

 Digital Object List

 Bookmark

No TOC