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Using Task Migration for Reducing On-Chip Communication Delay and Power Consumption in 3D NoCs

Yaghoubi, Hossein | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 41679 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. General-purpose Chip Multiprocessors (CMPs) are used to run a wide range of applications. Task-to-network mapping is one of the best NoC optimization methods which highly affects the NoC power and performance metrics. However, this kind of optimization can be applied
    only when the input application and its traffic pattern is known in advance and is described by a communication task-graph. However, for some applications, such as multimedia and network applications, the communication task graph is not known in advance. Hence, we cannot achieve an optimum task mapping by using the existing mapping algorithms. In this thesis, we aim to address this problem by proposing a distributed run-time mapping method for 3D-NoC based CMPs. In the proposed method, after an initial random mapping, the end point tasks of high-volume communication flows are moved to the nodes close to each other. In this approach, each task tries to find a proper network node as its migration destination by using a heuristic distributed algorithm. For the sake of avoiding the reduction in system performance, this algorithm is activated in certain intervals and is executed in parallel with the current task. Experimental results show that our proposal leads to considerable improvement in the average packet latency and network power consumption
  9. Keywords:
  10. Three Dimentional Network on Chip (NOC) ; Task Mapping ; Task Migration ; On-Chip Multiprocessor

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