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Statistical MPSoC Architecture Optimization under Process Variation

Ghorbani, Mahboobeh | 2010

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42046 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Goudarzi, Maziar
  7. Abstract:
  8. In nanometer technologies, the effect of process variation is observed in Multi-Processor System on Chip (MPSoC) in terms of variation in processors‟ frequency and leakage power. Traditionally, only worst case values of the system parameters were concerned and a worst-case optimization algorithm was employed for an application under design. As previous researches have shown these algorithms are not optimal in terms of parametric yield compared with newly employed statistical optimization algorithms. In this project, we have considered the problem of simultaneously selecting MPSoC architecture (which includes type and number of processors and the communication media) and task and communication scheduling in the selected architecture in order to optimize Energy-Yield of the manufactured chips under given timing constraint of the system. Two statistical optimization algorithms were proposed and implemented. First, statistical optimization by the Simulated Annealing algorithm and Monte Carlo method were developed and implemented on benchmarks. The implemented algorithm‟s results were compared by conventional worst-case method and superiority of them was shown in terms of Energy-Yield. Then, we improved the pseudo heuristic algorithm and proposed an Integer Linear Programming model for statistical optimization. This is the first attempt to formulate a statistical optimization algorithm by Integer Linear Programming which is a common optimization method. The proposed model was implemented on benchmarks and superiority of the statistical algorithm over conventional worst-case designs was shown.The statistical optimization model yields up to 23% improvement in terms of energy yield
  9. Keywords:
  10. Integer Linear Programming ; Process Variation ; Statistical Optimization ; Multi-Processor System on Chip Architecture ; Parametric Yield

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