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Design and Implementation of Fault-Tolerance Mechanisms for Scratch-Pad Memories (SPM) in Embedded Processors

Farbeh, Hamed | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42091 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. Energy consumption, area, reliability and predictability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories has an increasing role to satisfy these limitations. SPM as an on-chip SRAM memory is highly vulnerable to soft errors and as it contains the most frequently used blocks of the program, errors in SPM can easily propagate in system leading to erroneous results. This thesis proposes two approaches to protect the SPM against soft errors. The first approach, MM-SPM, proposed to protect the instruction SPM and the second approach, CR-SPM, proposed to protect dynamically mapped data and instructions to the SPM. The main idea behind the MM-SPM approach includes two stages: 1) using parity code for error detection in SPM, and 2) allocating a specific segment of the main memory as an SPM backup. Whenever an error is detected in SPM by the parity code, the error free entry is fetched from the backup in the main memory into SPM. Consequently, all errors that would be detected, can be corrected. Furthermore, as compared with single error correction/double error detection (SEC-DED) code, the experimental results show that the performance gain is improved by 51% and the energy consumption is decreased by 26% for a 4Kbyte SPM; moreover, the area overhead is 18% less than that of the SEC-DED protected SPM. CR-SPM protection approach is based on hardware-reuse in embedded system. Existing of both SPM and cache in the system, CR-SPM utilizes cache lines to store a backup copy of dirty SPM lines. Having a backup of clean lines in main memory and a backup of dirty lines in cache, it is possible to correct any detectable error in SPM. The expremintal results show that the speedup reduction is less than1.5% compared with non-protected SPM and the dynamic energy consumption overhead in cache is only 1.8%; moreover, the area overhead is also negligible compared to parity protected SPM.
  9. Keywords:
  10. Fault Tolerance ; Embedded Processor ; Scratch Pad Memory (SPM) ; Software Management

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