Sharif Digital Repository

Recent advances in VLSI technologies have enabled current silicon dies to accommodate billions of transistors in the design of very complex System-on-Chips (SoCs). To address the resulting complexity, Network-on-Chips (NoCs) have emerged as a paradigm to design scalable communication architecture to connect the processing cores of an SoC. However, smaller feature sizes, lower voltage levels and higher frequencies in Deep Sub-Micron (DSM) technologies make NoCs highly susceptible to transient faults, e.g., crosstalks, particle strikes, electro-magnetic interferences, and power supply disturbances. Single Event Upsets (SEUs) caused by high energy particle strikes as well as crosstalks are the... 

Nowadays, distributed embedded systems are extensively employed in safety-critical automotive applications, e.g. Steer-By-Wire and Brake-By-Wire. Moreover, according to the present and future needs of the automotive industry of Iran, in this Ph.D. thesis, fault tolerance in safety-critical distributed automotive communication networks has been improved. This thesis consists of three research layers. In the first layer, several comprehensive studies on all automotive communication protocols and their architectures have been done. Among the protocols, the FlexRay communication protocol has been selected to employ in safety-critical distributed embedded systems. In the second layer, the fault... 

The wide range of embedded processors and their reliance on nano-scale technologyhave brought them serious concerns on reliability, power consumption, timeliness and cost. Therefore, theseconcernsmust be addressed at the design process withemploying minimum facilities.This thesis proposes a low-cost concurrent error detection method based on control flow checking suitable for embedded processors. Most of the previous control flow checking methods either do not consider the embedded processors concerns, or they are not applicable to processors with on-chip cache memories.The key idea behind the proposed control flow checking method is to embed specific hardware components in the IP core of an... 

Energy consumption, area, reliability and predictability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories has an increasing role to satisfy these limitations. SPM as an on-chip SRAM memory is highly vulnerable to soft errors and as it contains the most frequently used blocks of the program, errors in SPM can easily propagate in system leading to erroneous results. This thesis proposes two approaches to protect the SPM against soft errors. The first approach, MM-SPM, proposed to protect the instruction SPM and the second approach, CR-SPM, proposed to protect dynamically mapped data and instructions to the SPM. The main idea behind the... 

Ever increasing applications of embedded systems have motivated designers to pay special atten-tion to the design requirements of such systems. Among embedded applications, safety-critical sys-tems have high reliability requirements as failures in such systems may endanger human life or re-sult in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. Reducing feature size, power supply voltage and also increasing operating frequency have increased the occurance rate of transient faults in such processors. Built in Self-Test facilities available in many of embedded systems forms about 70% of total cost in... 

One of the most important characteristics of real-time systems is executing tasks before their specified deadlines. The tasks’ execution may require several resources like processor, I/O ports, and data structures. Some of these resources may be shared between several tasks and their availability is important in executing tasks before the deadlines. Allocating shared resources which are used in mutually exclusive manner often encounteres some problems such as priority inversion and deadlock. Resource access protocols are used to minimize or eliminate these problems. The effect of using these protocols issupporting tasks’ execution before their deadlines. To meet deadlines is of decisive... 

Growth in the number of transistors on a single die has made Network-on-Chips more vulnerable to transient faults such as Crosstalks, SEUs and MBUs. The aim of this thesis is to evaluate the effects of virtual channel structures on the performance and the power consumptions of NoCs in the presence of transient faults. Evaluations have been carried out by different switch architectures and experimental conditions, i.e., different traffic and fault injection rates. In this regard, we have measured the power and latency of the switch both in different buffer allocation mechanisms and different switching methods. The evaluated switching methods in this work vary from Virtual Cut through (VCT) to... 

Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This thesis proposes a novel recomputation-based algorithm that efficiently protects SPM with high error... 

The development of embedded systems in safety critical applications leads to using fault tolerant methods to improve their dependability. Among the various fault tolerant methods, recently, software based methods are more appealing during to the following reasons: 1) They are applicable to the Commercial-Off-The Shelf (COTS) processors and lead to reduction in cost and time to market, 2) Unlike the traditional hardware based internal error detection methods, software based methods fault coverage are more promising, and 3)Software-based methods are cheaper, quicker and do not require any hardware modifications. The technology scaling trend in recent years, made system more vulnerable to... 

Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this study proposes an STT-RAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bit-lines of the tag update more. The SRAM part handles the... 

International Data Company (IDC) has reported, at the end of 2020, the total amount of digital data stored in the entire world will reach 40 thousand Exabytes. The idea of accessing this volume of data, anywhere at any time by exploiting commodity hardware, led into the introduction of cloud storage. The abounded rate and variety of failures in the equipment used in cloud storage systems, placed fault tolerance, at top of the challenges in these systems. HDFS layer in Hadoop has provided cloud with reliable storage. Replication is the conventional method to protect data against failures in HDFS. But the storage overhead is a big deal and therefore designers are tending towards erasure codes.... 

Bias Temperature Instability (BTI) is known as one serious reliability concern in nanoscale technology sizes. BTI gradually degrades threshold voltage (Vth) of MOS transistors. The main consequence of Vth degradation in SRAM cell transistors is the Static Noise Margin (SNM) degradation that makes SRAM cells susceptible against soft errors. SNM degradation in SRAM cells results in bit-flip occurrences and should be monitored accurately before resulting in permanent failures. This work proposes a sensor called Current-based BTI Sensor (CBS) to assess the aging state of SRAM cells. CBS measures BTI-induced SNM degradation of SRAM cells by monitoring the write current shifts due to BTI. The... 

Cache memories occupy a large portion of processors chip area. According to academic and industrial reports, the dominant effect of leakage current in less than 40-nm technology nodes has led to serious challenges in scalability and energy consumption of SRAM and DRAM memories. To overcome this challenge, different types of non-volatile memories have been introduced. Among them, Spin-Transfer Torque Random Access Memory (STT-RAM) memory is known as the best candidate to replace SRAM in the cache memories, due to its high density and low access latency. Despite their advantages over SRAMs, several problems in STT-RAM need to be addressed to make it applicable in cache memories. The most... 

In recent years we have witnessed a growth in handheld or wearable technologies among others, which have tested the limits of SRAM. The technological advancements of recent years and a persistent trend in reduced feature sizes have been testing the limits of SRAM for quite a while. It is becoming clear that because of high leakage the SRAM technology does not satisfy the ever increasing demand for reduced cost and dimensions, and, as a result Non-Volatile Memory with lower leakage property is a promising alternative to bridge the aforementioned gaps. But limited endurance is one of its weaknesses.In this paper we propose a novel method dubbed “online write-prevention coding” to incorporate... 

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most affected modules by NBTI. Variations in duty Cycles and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes... 

Wireless Sensor Networks (WSN) are wildly utilized in surveillance and controling applications, and because of their remote and standalone operation, lifetime and reliability of a typical WSN are two main concerns in these networks. One of the reliability threatening issues in a WSN is residual accessible energy for each node. Nowadays, energy harvesting systems are used in WSN nodes to catch environmental energy, and reduce the energy limitation. However, because of inherent uncertainty of energy harvesting systems, the networks that operate using environmental energy have new reliability issues. Different rate of energy harvesting, according to environmental conditions, is one of the most... 

Technology node scaling in recent decades ushered in gate delay cut-off and rise of interconnection latency. Hence, interconnects have become a major performance bottleneck of high performance system-on-chips (SoC) and integrated circuits (IC). In addition, interconnectiosns have become more susceptible to noises in particular crosstalk. On the other hand, the advent of multi-core processors with ever increasing number of cores has highlighted the need for fast and reliable interconnections. One of the potential solutions to alleviate the interconnection delay problem is the three dimensional integration using through-silicon vias (TSV). Vertical integration of IC dies using TSVs offers high... 

Reliability is an important concern in safety-critical applications. Hardware and software redundancies are used to include reliability in such systems. Software approaches benefit from high flexibility and low cost. Moreover, they do not impose any hardware modifications to the design. The most important challenges of software approaches are performance and code size overheads. Some of software reliability approaches duplicate all of the program’s instructions which impose high performance overhead to the designs. Some other approaches only apply the redaduncies to critical instructions in the programs. While these approaches impose the the performance overhead but they suffer from fault... 

Use of nano-scale VLSI technologies in the fabrication of System-on-Chips (SoCs) makes reliability as one of the major issues in the design and implementation of these products. SoCs are susceptible to several fault sources such as crosstalks, cosmic particle strikes, electromagnetic interferences, and power supply disturbances. Among the mentioned fault sources, crosstalks have the major contribution in threatening the reliability of SoCs. This thesis addresses the modeling and mitigation of crosstalk faults. In this regard, two analytical models and three crosstalk reduction methods have been introduced. The proposed analytical models, which have been introduced in the fourth chapter of... 

Dependability assessment is an important preliminary in the design of dependable systems. Simulation Based Fault Injection (SBFI) is a common way to evaluate system dependability. To achieve high accuracy in SBFI, a large amount number of fault injection is required, which is very time consuming. Many of ideas are implied to solve this disadvantage of SBFI. In this work, we propose a method that uses information of workload execution on the processor to reduce faults to be injected during the SBFI campaign. We concentrate on Single Event Upsets because of its majority and repeating interval. Our proposed method first gathers information about various regions of the processor by probing...