Loading...
| Friend's email | |
| Your name | |
| Your email | |
| enter code | |
This page was sent successfuly
- Type of Document: Ph.D. Dissertation
- Language: Farsi
- Document No: 41784 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Miremadi, Ghassem
- Abstract:
- Recent advances in VLSI technologies have enabled current silicon dies to accommodate billions of transistors in the design of very complex System-on-Chips (SoCs). To address the resulting complexity, Network-on-Chips (NoCs) have emerged as a paradigm to design scalable communication architecture to connect the processing cores of an SoC. However, smaller feature sizes, lower voltage levels and higher frequencies in Deep Sub-Micron (DSM) technologies make NoCs highly susceptible to transient faults, e.g., crosstalks, particle strikes, electro-magnetic interferences, and power supply disturbances. Single Event Upsets (SEUs) caused by high energy particle strikes as well as crosstalks are the main faults that may occur in an NoC. SEUs produce unwanted bit flips in the memory elements of NoCs which are called soft errors. Crosstalks happen because of coupling capacitances formed between adjacent wires of communication channels in NoCs. The coupling capacitances may result in undesired transition on a victim wire when desired transitions appear on the neighboring wires of the victim wire. Such coupling capacitances have negative impacts on delay, signal integrity of data transmission, and power consumption in NoCs.
This thesis addresses soft errors and crosstalk faults in NoCs. In this regard, soft error and crosstalk fault have been analytically modeled to precisely study their impacts on NoCs. Using this modeling, efficient mitigation/elimination methods have been proposed to tackle the problem of soft errors and crosstalk faults. Soft error mitigation is achieved by the use of complement routing as well as the soft error tolerant switch architecture proposed in this thesis. The key idea behind complement routing methodology is the concept of complement routing in which two routing algorithms with disjoint sets of allowed turns are incorporated. According to this methodology, while a packet is routed by a routing algorithm, a redundant copy of that packet is routed by the complement of that routing algorithm. To find the complement of the used routing algorithm, an analytical approach based on the channel dependency graph has been presented. The proposed soft error tolerant switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The architecture creates a redundant copy of each recently received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit.
Crosstalk faults in NoC have been addressed by a power-efficient flow-control method. The method combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a sequence of flit which produces the lowest number of OD transitions in NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of OD transitions. Finally, the third mechanism called flit-insertion, investigates flits of the packet to find the OD transitions which are not removed by the first and second mechanisms. This mechanism inserts null-flits between the required flits to completely eliminate appearance of OD transitions on NoC channels. In addition a numeral-based crosstalk avoidance coding is proposed in the thesis to protect communication channels of NoCs against crosstalk faults. This coding produces codewords without ‘101’ and ‘010’ bit patterns to eliminate harmful transition patterns from NoC channels. The proposed numeral system, 1) can be utilized in NoC channels with any arbitrary width, and 2) can be implemented with low area, power, and timing overheads. HDL and Spice simulations reveal that the coding completely removes crosstalk faults from NoC channel.
All proposed methods in this thesis are evaluated by both experimental and analytical approaches. Experimental evaluations are done using various HDL and Spice simulations to extract power, area and timing overheads of the proposed methods. Also, the methods are compared with those previously presented in the literature. Experimental evaluations of the proposed methods reveal significant improvements in the reliability of NoCs. In addition to experimental evaluations, analytical approaches have been used to evaluate the proposed methods of the thesis. The analytical approaches can be used to achieve a noticeable speed-up in the evolution of the soft error and crosstalk mitigation methods. According to evaluations, presented models can help designers to preseicely study the effects of soft errors and corsstalk fautls in NoCs, and presented methods efficiently improve the reliability of NoCs against soft errors and crosstalk fautls - Keywords:
- Network-on-Chip (NOC) ; Analytical Modeling ; Fault Tolerance ; Crosstalk Fault ; Soft Error
Digital Object List
-
محتواي پايان نامه
- view
Bookmark