Investigation of the Effects of Aging and Process Variation on Reliability in SRAM Based Memory Circuits

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Nazari, Reza | 2014

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 46184 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Miremadi, Ghassem
Abstract:
Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most affected modules by NBTI. Variations in duty Cycles and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes uniformly stress condition for each line. The simulation results show that the proposed technique reduces the NBTI effect in I-cache significantly as compared to normal operation. Moreover, the energy consumption and the performance overheads of the proposed technique are negligible
Keywords:
Reliability ; Cache Memory ; Aging ; Process Variation ; Fault Tolerance ; Static Random Access Memory (SRAM)Cell ; Memory Cells

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