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Including Facilities in an Embedded Processor for External Watchdog Processors

Khosravi, Faramarz | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42092 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. The wide range of embedded processors and their reliance on nano-scale technologyhave brought them serious concerns on reliability, power consumption, timeliness and cost. Therefore, theseconcernsmust be addressed at the design process withemploying minimum facilities.This thesis proposes a low-cost concurrent error detection method based on control flow checking suitable for embedded processors. Most of the previous control flow checking methods either do not consider the embedded processors concerns, or they are not applicable to processors with on-chip cache memories.The key idea behind the proposed control flow checking method is to embed specific hardware components in the IP core of an on-chip memory based embedded processor in order to facilitate error detection using an external watchdog processor. The proposed on-chip hardware discovers branch instructions and generates runtime signatures. When this hardware detects a commitment of a branch instruction, it sends the branch source and destination addresses, and the signature of the last executed program basic block on the external bus of the system using a FIFO buffer.The watchdog processorwhichmonitors the external bus, receives the signature and its corresponding branch addresses,and then compares them with the reference golden model stored in its local memory to detect potential control flow errors. Based on our experimental results, the proposed method detects more than 96.7% of control flow errors with only 1.44% overhead in area and less than 1% increase in power consumption. Moreover, the proposed method imposes almost no performance degradation and no memory overhead in the main processor, whilehavingthe error detection latency of less than 76 instruction cycles
  9. Keywords:
  10. Embedded Processor ; Concurrent Error Detection ; Control Flow Checking ; External Watchdog Processor

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