Loading...

Interconnect Modeling, Its Step Response Analysis and Introducing Fast Look up Tables for Propagation Delay and Bit rate in VLSI Applications

Mehri Sookhtekoohi, Milad | 2011

590 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42101 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sarvari, Reza
  7. Abstract:
  8. In this thesis we study circuit models and their step responses of the Interconnects. First of all, we solve the Maxwell’s equations for lossless line to understand the models deeply and then generalize it for lossy lines. Only with equations that govern the model, one can realize the regions in which his model behaves correctly. After that, the transfer function of a single line with arbitrary load and source impedance is derived, based on lossy segmented model. Knowing this, we introduce different methods of getting the inverse Laplace of transfer function and their pros and cons. Finite pole approximation, Fourier series harmonics, and changing variable are various methods to simplify transfer function. A new method of decreasing the number of transfer function variables is introduced, which named Normalization. Normalizing a line with capacitive load and resistive source impedance can reduce six variables of the transfer function to three variables. Having normalized line, we simulate it with HSPICE to obtain propagation delay and bit rate of the line for a vast range of normalized variables. These ranges fully cover the Interconnects normalized variable used in VLSI. To generate a fast accessible look up table, LUT, we introduce three sampling methods. Apply these algorithms to simulated data, produces very simple and small LUT with 7/7% maximum and 1/0% in average error, rather than HSPICE data. LUTs are very popular in CAD tool because of easy application and accessibility rather complicated formulas. Also, with curve fitting of simulated data, we derived simple formula for bit rate estimation by respecting skin effect and dc resistance of the line for VLSI application. At the end, we model driver of line, a buffer gate, with alpha power model for MOS transistor. We derive equations for output resistance of the minimum buffer size and generalized relation for a given size buffer. In addition, the overshoot and undershoot of the buffer, due to zero in transfer function, is investigated carefully, with familiar circuit model of the buffer.
  9. Keywords:
  10. Maxwell Equations ; Propagation Delay ; Sampling ; Bit Rate ; Inter Connects ; Look Up Table (LUT)

 Digital Object List

 Bookmark

No TOC