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A Post-Processor for Control Flow Checking of Jump and Branch Instructions

Farhady Ghalaty, Nahid | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42234 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. Ever increasing use of embedded systems has made them an inevitable part of human life. In 2006, more than 76% of fabricated microprocessors were used in embedded systems. On the other hand, the most important applications for embedded systems are the safty-critical applications and failure in these systems can ba catastrophic. Nowadays, the probability of transient faults has been increasing 8% with coming of the new age of fabrications. So, dependability has been an important concern for the desginers. Control flow checking has been one of the most important ways of avoding failurs.in this thesis a software control flow checking method has been introduced. This mechanism is based on branch instruction triplication. Betwwen the branch instructions software trap routins are used to check the correctness of the instructions. If there was a mismatch between instructions a fault is reported. In control flow checking methods a post processor is usually used that inserts instructions to the assembly code of the program. The problem here is that inserting instructions can cause a mismatch in the address of branch instructions. For the direct branch instructions, by counting the number of insterted instructions and adding them to the destination address, the problem is solved. But, for indirect instructions, there must be a run time algorithm, because the destination addresses aredetermined runtime. An algorithm is proposed in this thesis for this problem. The results of simulation showed that this method is capable of error detecting and correcting coverage for 96% of faults, with 13 instructions delay. The code size overhead is about 27.8% and the performance loss is about 13.9%.
  9. Keywords:
  10. Postprocessors ; Control Flow Checking ; Indirect Branch Addressing

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