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Hardware Redundancy in Fault-Tolerant Digital Systems: A VHDL Approach to Evaluate TMR Robustness

Samsami Khodadad, Farshid | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: English
  3. Document No: 42562 (55)
  4. University: Sharif University of Technology, International Campus, Kish Island
  5. Department: Science and Engineering
  6. Advisor(s): Jahed, Mehran
  7. Abstract:
  8. Triple Module redundancy (TMR) is a commonly used approach to increase reliability in space applications. Applying this method, triple modules and voting circuits are implemented in a field programmable gate array (FPGA). In TMR systems when a single event upset (SEU) occurs, the voting circuit neglects the failure value of a module receiving the SEU and takes a correct value from the other two modules. The present TMR approach utilized for the combinational and sequential logic on the gate level shows that it is possible to write hardware description language (VHDL) code in a structured yet high level coding style to obtain the required redundancy. However using VHDL, the level of required protection is actually not determined. This can only be derived from a characterization of the fault, namely reliability and the area of each sub module. For Cascading TMR Systems, in order to utilize an optimal system configuration that maximizes reliability and minimizes area, one must evaluate very large number of system configurations. To alleviate this hurdle a novel genetic algorithm was introduced. This Optimization approach provided a Cascading TMR System Configuration that maximizes reliability and minimizes required area
  9. Keywords:
  10. Fault Tolerance ; Hardware Redundancy ; Reliability ; Optimization ; Very Highspeed Integrated Circuits Hardware Description Language (VHDL) ; TMR Method

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