Loading...

Design of Fault Tolerant Processor for Implementation on SRAM Based FPGAs

Ghaderi, Zana | 2012

566 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43946 (19)
  4. University: sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the system in HAFTA, a history flip-flop is considered for each flip-flop. To reduce power and area, the unused flip-flops available throughout SRAM-based FPGAs are employed as history flip-flops. Upon detection of any mismatch between the main and replica flip-flops, the entire design is able to roll-back to the latest correct state stored in the history flip-flops. Repetition of roll-back in consecutive clock cycles indicates the presence of permanent fault(s) in the system; in this case HAFTA triggers partial reconfiguration signal to correct fault(s). To implement HAFTA, a CAD tool is developed using C# language. This tool trasforms target circuit architecture (Processor, controller …) to HAFTA. This is done in the place and route level. Moreover, the tool is able to be embedded on commercial SRAM-based FPGA CAD tools. The simulation results extracted using fault injection experiments demonstrates that failure rate in HAFTA is equal to zero at 95% confidence level, while failure rates in coarse grain and fine grain TMRs are about 34% and 12%, respectively. Availability of HAFTA is two orders of magnitude more than TMR. The dynamic power consumption overhead in coarse grain and fine grain TMR are 70% and 101% more than HAFTA, respectively. These ratios are about to 31% and 73% for area overhead
  9. Keywords:
  10. Availability ; Fault Tolerance ; Soft Error ; Field Programmable Gate Array (FPGA) ; Static Random Access Memory (SRAM)Cell

 Digital Object List

 Bookmark

No TOC