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Design of Robust Digital Circuits Against Soft Errors Considering Multiple Event Transients Fault (METs)

Rezaei, Siavash | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44031 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. Nowadays, one of the most important challenges in the design of digital circuits is their susceptibility to the strike of high energy particles which leads to the Single Event Transient (SET) and Multiple Event Transients (MET). In fact, technology scaling which results in lower supply voltage, higher operating frequency, and lower nodal capacitance, makes today’s digital circuits more susceptible not only to high energy particles but also to low energy particles. Moreover emerging deep sub-micron technologies and the integration of more cells in today’s chips have caused higher probability of MET occurrences. A lot of research has tried to reduce the soft error rate due to high energy particles bombarding the combinational parts of digital circuits. Almost all of this research has concentrated on the soft errors originating from SET. This thesis proposes a method to reduce the soft error caused by both SET and MET in digital circuits. The proposed method is based on the gate sizing approach and combines two techniques, called technique A and technique B in this thesis, to identify more susceptible gates. In technique A, the susceptibility of each gate against particle strikes is determined by considering the signal probability of its inputs. This helps us to achieve considerable reduction of the SET rate by hardening the most susceptible gates of the digital circuits. Simulation results show that the efficiency of technique A is reduced as the probability of MET occurrences is increased. To keep the efficiency level, technique B is proposed which select appropriate gates locally by considering the susceptibility of neighboring regions in the chip. Finally, by using zero overhead input reordering method, a more considerable reduction for soft error rate caused by SET and MET is achieved. To implement the proposed method, an automation tool is developed as shown in Figure 1. The inputs of this tool are HSPICE simulation results and ISCAS'89 circuits. The method is evaluated using a statistical analysis approach. The results show an average of 64% reduction in soft error rate caused by SET and MET with 2% area overhead and no delay overhead
  9. Keywords:
  10. Soft Error ; Fault Tolerance ; Radiation Hardening ; Single Event Transient Error ; Multiple Event Transient Error

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