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Evaluating the Energy Consumption of Fault-Tolerance Mechanisms In Processors Implemented on Sram-Based Fpgas

Yousefizadeh Naeini, Mohammad Reza | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44094 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. The soft errors vulnerability of SRAM-based FPGAs limits their usage in safety-critical applications. Moreover, the rate of multiple soft errors increases due to the feature size reduction. Hence, this issue becomes a challenge against reliability of the implemented circuit on SRAM-based FPGAs. Appealing to specifics such as low cost and re-configurability in SRAM based FPGAs provide this ability to change implemented design remotely. This advantage is not negligible in safety critical applications such as space, military, etc. Several mechanisms have been purposed to design fault-tolerant and resilient system based on FPGAs. Fault tolerance is usually achieved by adding redundancy to the system. These redundancies impose significant cost area and power consumption overhead to the system. In this work, we have evaluated the energy consumption overhead of three common fault-tolerance schemes and compare them to each other. These schemes include TMR, DWC with Re-execution, and temporal redundancy. These schemes are implemented in the ALU of LEON 2 processor. There are two ways to evaluate energy consumption in FPGAs; energy estimation and energy measurement. The accuracy of estimation models is highly dependent on the accuracy of the method used for their characterization. The highest precision is achieved by using physical onboard measurements. In this work, we use a measurement methodology for power and energy evaluation. The results of this thesis show that energy overhead of DWC with Re-execution is 1.7, TMR is 2.5 and temporal redundancy is 2.7 as compared to the plain processor. The assessments in this work can help system designers to understand the energy efficiency of different schemes and the trade-offs associated with the system specification
  9. Keywords:
  10. Energy Consumption ; Fault Tolerance ; Static Random Access Memory (SRAM)Cell ; Field Programmable Gate Array (FPGA)

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