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Design of Fault Tolerance Mechanisms for Scratchpad Memories in Multi-core Embedded Systems

Delshad Tehrani, Leila | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44734 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. The increasing need of processing power and low power computation in embedded systems is leading to the deployment of multi-core embedded systems. One important constraint in real-time embedded systems is their predictable behavior. To meet this constraint, scratchpad memory (SPM) is introduced. SPM as an on-chip SRAM memory is highly vulnerable to soft errors. As on-chip memories (SPM and cache) contain the most frequently used blocks of the program, hence errors in them can easily propagate in the system leading to erroneous results. Employing traditional mechanisms such as ECC to protect SPM incur significant power and performance overheads and therefore they are not efficient for many of embedded systems. This issue is more serious when using in multi-core embedded systems. This thesis proposes a different method to protect SPMs in multi-core embedded systems, called In-Scratchpad Memory Replication (ISMR). The idea is based on data block replication, in which the replication of a data block is stored within the local or a remote SPM. To do this, during the execution of the program the active and vulnerable data blocks are recognized based on the analysis of the program behavior and data access patterns. Then, inactive data blocks are used to store the replication of active data blocks. The proposed method uses parity code to detect errors and corrects them using the replication. The Simics simulator is used for the implementation and the Synopsys Design Compiler and CACTI are used for the evaluation of the method. As compared with single error correction/double error detection (SEC-DED) code, the experimental results on ParMiBench benchmarks show that the proposed method incurs 8% and 12% less performance overhead for 4-core and 8-core embedded systems, respectively. This method incurs 7% and 9% less energy consumption overhead in comparison to SEC-DED code for 4-core and 8-core embedded systems, respectively. Furthermore, all errors detected with parity code could be corrected, while the SEC-DED code could only correct single bit errors
  9. Keywords:
  10. Fault Tolerance ; Scratch Pad Memory (SPM) ; Multicore Embedded System ; Data Replication

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