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Influential Factors in the Unstability of SRAM Cell and a Novel Structure for Improvement of Stability

Hasanzadeh, Sina | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 46140 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Hajsadeghi, Khosro
  7. Abstract:
  8. Embedded SRAM unit is recognized as an important block in the systems on chip. In recent years due to an abrupt increase in the number of such systems which often work with battery, the priority of designing of low power circuits has been increased. Furthermore, increase in the number of transistors in the SRAM and increase in leakage current of MOS transistors with technology scaling have rendered the SRAM into the main energy consumer (from both static and dynamic view).In the writing operation due to the full swing of bit line, the dynamic power forms the main chunk of the consumptive power. The static consumptive power mostly happens due to the leakage current of broken cells in an array and this phenomenon often occurs at the sub-threshold region.in recent years one of the main solutions for the decrease of consumptive power is decrease in the supply voltage. But when the supply voltage is decreased in order to decrease the consumptive power, the stability of the stored data in the SRAM cell is became an important challenge. In this dissertation the influential factors in stability of a SDRAM and consumptive power of a SRAM is investigated, Also some structures are proposed for increase in stability an decrease in consumptive power of a cell .the new structures are simulated for a 0.3V supply voltage. In the reading operation, the proposed structure with 8 transistors increases the margin of the static noise 90% in a comparison to the commonplace structure with 6 transistors, while it doesn’t change the margin of the dynamic noise in the writing operation and holding. Note that the proposed structure has passed the DRC, LVS and RC Extract phases and has only 50% increase in the occupied area toward the structure with 6 transistor while other structure which are represented at the sub-threshold region have more increase in the occupied area. This structure needs a lower consumptive power and has simpler circuit topography due to need of lesser control signals. 32 kilobit of structure with 8 transistors is simulated and is embedded in the 90nm technology layout. The memory and other related circuits occupy 0.326 mm2, all together
  9. Keywords:
  10. Stability ; Subthreshold ; Static Random Access Memory (SRAM)Cell

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