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Fault Tolerant Routing in Wireless Network on Chip

Tavakoli, Ehsan | 2014

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 46497 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Tabandeh, Mahmoud; Raahemi, Bijan
  7. Abstract:
  8. Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantage of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the ITRS annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the operating frequency of RF devices increases, the size of Si integrated antenna will decrease and it is feasible to employ them as a revolutionary interconnect for intra-chip wireless communications. In this research, we focus on physical requirement and design challenges of wireless NoC. It is demonstrated that employing an optimum-radiation phased array antenna and multihop communications will increase the reliability of on-chip wireless links by several orders of magnitude using a limited power budget less than 1 pJ/bit.
    We, also, designed and analyzed a flexible wireless medium access control protocol named WMAC for on-chip wireless application. WMAC is a simplified and optimized version of the well known MACAW and IEEE 802.11 DCF mode protocols for wireless multi-hop networks. Due to spatial reuse of the spectrum, RF nodes sufficiently far apart can transmit concurrently and the network throughput will be increased compared to the single hop communications counterpart design. The performance of WMAC is evaluated in an M×N Mesh wireless network-on-chip (MWNoC). Simulation and synthesis results demonstrated several prominent features such as low power consumption and low area cost of the WMAC which is less than 0.4% in a SoC based IC
  9. Keywords:
  10. Network-on-Chip (NOC) ; Wireless Network-On-Chip (WNoC) ; Fault-tolerant Routing ; Antenna on Chip ; Wireless Medium Access Control (WMAC) ; Wireless Routing Algorithm ; Multihop Communication ; On-Chip Wireless Link

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