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P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs

Bashizade, R ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1016/j.vlsi.2014.11.002
  3. Abstract:
  4. Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our experimental results show that the proposed scheme can beat the state-of-the-art arbiter design by up to 12.5% and 6.8% in terms of saturation rate and zero-load latency, respectively, under synthetic traffic patterns. These results also demonstrate a 29.5% improvement in average packet latency in Splash-2 applications in favor of P2R2 with respect to the state-of-the-art arbiter
  5. Keywords:
  6. Arbitration ; Network-on-chip ; Parallel Pseudo-Round-Robin arbiter ; Asynchronous sequential logic ; Clocks ; Microprocessor chips ; Routers ; VLSI circuits ; Average packet latencies ; Chip multi-processors (CMPs) ; Clock frequency ; Round Robin ; Traffic pattern ; Virtual channels
  7. Source: Integration, the VLSI Journal ; November , 2014 ; ISSN: 1679260
  8. URL: http://www.sciencedirect.com/science/article/pii/S0167926014000819