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Circuit Level Techniques for Soft Error Mitigation in Combinational and Sequential Parts in Nano-scale CMOS Technology

Rajaei, Ramin | 2013

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 46898 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Tabandeh, Mahmoud; Fazeli, Mahdi
  7. Abstract:
  8. CMOS technology has reached two digit nanometer dimensions. This scaling trend improves performance and power consumption on the one hand, and reduces noise margin and circuits reliability on the other. Along with downscaling, sensitivity to radiation induced soft errors is increasing. As CMOS dimensions are shrinking, node capacitance of circuits become smaller. Consequently, particles with smaller charge could induce parasitic voltages in some nodes and result in soft errors. There are more particles with smaller charge than the ones with larger. Therefore, soft error rate is rapidly increasing with technology advances. Single Event Multiple Effects (SEMEs) is a new challenge emerged in nanometer CMOS circuits. In this type of soft errors, a particle affecting the hit node, would also affect adjacent node(s) and result in multiple effects. Process variation is another concerning challenge in VLSI design that could affect functionality and reliability of the circuits. In this dissertation, robustness of the sequential as well as combinational logic circuits against radiation induced soft errors has been improved suggesting new circuit design. To improve the robustness, SEMEs are considered as new reliability challenge. Also, process variation effects are investigated. In combinational logic, more susceptive gates are identified using a proposed soft error propagation probability method. Then, using two proposed soft error protection techniques (one for preventing occurrence and another for masking the occurred soft errors), we protected combinational logic circuits against soft errors. For sequential logic, proposing three different latch circuits with unique capabilities we could improve robustness of this section of digital circuits against soft errors. In another part of this research, we proposed two low cost and soft error tolerant SRAM cells and improved robustness of memory logic. Along with proposed radiation protection techniques and circuits, we showed that the new emerging non-volatile STT-RAM technology is still vulnerable to radiation soft errors during read operation. We also proposed two magnetic STT-latch circuits that are capable of fully tolerating single event upsets as well as highly robust against SEMEs
  9. Keywords:
  10. Soft Error ; Process Variation ; Single Event Upset (SEU)Error ; Single Event Transient Error ; Multiple Event Transient Error ; Complementary Metal Oxide Semiconductor Technology (CMOS) ; Single Event Multiple Upset (SEMU)Error ; Magnetic Based Memories

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