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An Efficient Reconfigurable Architecture Based on Most Frequent Logic Functions

Ahmadpour Yasouri, Iman | 2015

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 47207 (19)
  4. University: Sharif University of Technology
  5. Department: Mechanical Engineering
  6. Advisor(s): Asadi, Hossein
  7. Abstract:
  8. Reconfigurable devices are a popular platform invarious computational fields due to having high performance and flexibility and low non-recurring engineering cost. Generous flexibility of Look-up Tables (LUTs) in implementing arbitrary functions comes withsignificant area and performance overheads as compared with their Application Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this thesis, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL).Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAs, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAs
  9. Keywords:
  10. Look Up Table (LUT) ; Reconfigurable Architecture ; Application Specific Integrated Circuit (ASIC) ; Logic Block ; Area ; Versatile Placement and Routing (VPR)Tools

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