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Prolonging Lifetime of the Last-Level Non-volatile Cache in Multicore Processors by Separating Tag and Data Arrays

Behroozi, Setareh | 2015

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 47297 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. Due to serious challenges of SRAM based caches in sub-micron region, researchers seek for new alternatives. Among the proposed options, STT-RAM seems to be a promising candidate. STT-RAMs with high density, low static power consumption and proper scalability open a new door to respond to future demands. But, unfortunately adopting these type of memories coupled with the limited number of write operation and consequently short lifetime issue. Hence, for practical usage of these type of memories, we must address the short lifetime problem efficiently. This way, using a decoupled caches structure which provide better opportunity of relocation, we propose Caribou to extend the lifetime of STT-RAM based system. More clearly, by detecting hot blocks in the cache which are in minorities, we relocate them to cold locations in order to reduce the stress of write operations on specific line location. Additionally, employing a rotation based mechanism we address the problem of intra-block variation effectively. The full-system simulation results reveal that Caribou enhance the lifetime of the system 460% and 220% compared to state-of-the-art systems; i2wap and sequoia, respectively along with 1.86% miss rate degradation
  9. Keywords:
  10. Last Level Cache (LLC) ; Nonvolatile Memory ; Wear Leveling ; Life Time Constraint ; Separating Tag & Data Arrays

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