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A novel low power 8T-cell sub-threshold SRAM with improved read-SNM

Hassanzadeh, S ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/DTIS.2013.6527774
  3. Publisher: 2013
  4. Abstract:
  5. The fast growth of battery-operated portable applications has compelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the sub-threshold regime many structures has been proposed adding extra transistors to the conventional 6T-cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is simple. The new structure uses fewer controlling signal in comparison to the conventional 8T-cell SRAM. Thus, the proposed 32k SRAM consumes 25% lower power consumption in the read operation for 0.3V sub-threshold SRAM in 90nm TSMC CMOS model
  6. Keywords:
  7. SRAM ; Stability ; Sub-threshold ; Differential output ; Lower-power consumption ; Portable applications ; Static noise margin ; Static random access memory ; Sub-threshold SRAM ; Subthreshold ; Subthreshold operation ; Convergence of numerical methods ; Integrated control ; Nanotechnology ; Static random access storage ; Structural design ; T-cells
  8. Source: Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 ; 2013 , Pages 35-38 ; 9781467360388 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6527774