Loading...

Hierarchical opto-electrical on-chip network for future multiprocessor architectures

Koohi, S ; Sharif University of Technology | 2011

1287 Viewed
  1. Type of Document: Article
  2. DOI: 10.1016/j.sysarc.2010.07.003
  3. Publisher: 2011
  4. Abstract:
  5. Importance of power dissipation in NoCs, along with power reduction capability of on-chip optical interconnects, offers optical network-on-chip as a new technology solution for on-chip interconnects. In this paper, we extract analytical models for data transmission delay, power consumption, and energy dissipation of optical and traditional NoCs. Utilizing extracted models, we compare optical NoC with electrical one and calculate lower bound limit on the optical link length below which optical on-chip network loses its efficiency. Based on this constraint, we propose a novel hierarchical on-chip network architecture, named as H2NoC, which benefits from optical transmissions in large scale SoCs and overcomes the scalability problem resulted from lower bound limit on the optical link length. Performing a series of simulation-based experiments, we study efficiency of H2NoC along with its power and energy consumption and data transmission delay. Furthermore, the impact of network size, traffic pattern, and packet size distribution on the prominence of the proposed architecture over traditional NoC and non-hierarchical ONoC is addressed in this paper. Our experimental results verify that the proposed hierarchical architecture outperforms non-hierarchical ONoC for moderate and large scale MPSoCs, while its prominence degrades for small number of processing cores
  6. Keywords:
  7. Optical NoC ; Analytical model ; Contention-free ; Data transmission delay ; Energy consumption ; Hierarchical architectures ; Hierarchy ; Its efficiencies ; Lower bounds ; Multi processor architecture ; Network size ; New technologies ; On-chip interconnects ; On-chip networks ; On-chip optical interconnects ; Optical networks ; Optical NoC ; Optical transmissions ; Packet size distribution ; Power consumption ; Power dissipation ; Power reductions ; Processing core ; Proposed architectures ; Scalability problems ; Simulation-based ; Traffic pattern ; Electric losses ; Energy utilization ; Fiber optic networks ; Light transmission ; Mathematical models ; Optical interconnects ; Optical links ; Scalability ; VLSI circuits ; Network architecture
  8. Source: Journal of Systems Architecture ; Volume 57, Issue 1 , 2011 , Pages 4-23 ; 13837621 (ISSN)
  9. URL: http://www.sciencedirect.com/science/article/pii/S1383762110000706