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Buffer Modeling and Optimization for NSoLT (Near Speed of Light Transmission)in Future Technologies

Shahhosseini, Sina | 2015

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48045 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sarvari, Reza
  7. Abstract:
  8. As the transistors’ dimensions in integrated circuits shrink, according to Moore’s law, a number of challenges emerges that can decrease the benefits of scaling. One of the main challenges in deep submicron CMOS technologies is the delay in interconnects. In recent years, researchers have been looking into different methods to minimize the delay in interconnects. International Technology Roadmap for Semiconductors (ITRS) predicts that the input capacitance of a buffer will become in the order of 10s of aFs with technology scaling. This will give us the opportunity to transmit the data in electrical interconnects near the speed of light.In this thesis, a novel buffer is designed in which the buffer’s delay is only a small fraction of the total propagation delay of the signal on the transmission lines in global interconnects on digital integrated circuits. In the design of the buffer, some of the electrical parameters such as on-resistance and the input capacitance are considered. Different buffer configurations are investigated using the technology parameters of a 7-nm FinFET CMOS technology. A small number of these configurations is usable because in most cases the voltage at the end of the line. After finding the possible configurations, the length of the transmission line is swept to find the optimum configuration. By comparing the delay, total power consumption, occupied area, and transistor parameters’ sensitivity to process variations, the optimum buffer at the optimum length is found to replace the conventional repeaters. As a result of this simulation, a buffer is designed which its delay is 1.36 times of electrical signal time of flight on a transmission line. In the design of this buffer, the delay is considered as the most important parameter. It is also shown that with 12% increase in the buffer delay, the power consumption and occupied area are reduced by 45%. Moreover, the sensitivity of the buffer to process variations is discussed. Finally, it is shown that the variation in the optimum delay in buffers is mostly because of the power supply variation in comparison with other parameters
  9. Keywords:
  10. Data Transmission ; Buffers ; Time of Flight ; Electrical Interconnect ; Light Speed

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