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A novel area-efficient VLSI architecture for recursion computation in LTE turbo decoders

Ardakani, A ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSII.2015.2407232
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2015
  4. Abstract:
  5. Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing. In this brief, a novel relation existing between the α and β metrics is introduced, leading to a novel add-compare-select (ACS) architecture. The proposed technique can be applied to both the precise approximation of log-MAP and max-log-MAP ACS architectures. The proposed ACS design, which is implemented in a 0.13-μm CMOS technology and customized for the LTE standard, results in, at most, 18.1% less area compared with the reported designs to date while maintaining the same throughput level
  6. Keywords:
  7. Add-compare-select (ACS) unit ; Long-term evolution (LTE) ; parallel architecture ; Recursion unit ; Turbo decoder ; Very-large-scale integration (VLSI) ; Channel coding ; CMOS integrated circuits ; Decoding ; Integrated circuit testing ; Iterative decoding ; Iterative methods ; Parallel architectures ; Throughput ; Turbo codes ; VLSI circuits ; Wireless telecommunication systems ; Add-compare-select ; Channel coding schemes ; Iterative decoding algorithm ; Next-generation wireless communications ; Radix-4 ; Recursions ; Turbo decoders ; VLSI architectures ; Long Term Evolution (LTE)
  8. Source: IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 62, Issue 6 , 2015 , Pages 568-572 ; 15497747 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7047776/?arnumber=7047776