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Fast architecture for decimal digit multiplication

Fazlali, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1016/j.micpro.2015.01.004
  3. Publisher: Elsevier , 2015
  4. Abstract:
  5. Abstract BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication scheme to accelerate this module. Similar to previous articles, our multiplier includes two parts contained binary multiplier and binary to BCD converter. Our contribution towards these modules can successfully overcome the previous BCD digit multipliers. The results indicate 19% hardware acceleration for the proposed multiplier architecture which is comparable to the best previous techniques in UMC 65 nm CMOS standard cells library hardware implementation. Therefore, the proposed BCD digit multiplier is an appropriate candidate to be utilized in BCD arithmetic units
  6. Keywords:
  7. Binary coded decimal (BCD) encoding ; Binary to BCD conversion ; Computer hardware ; Digital arithmetic ; Binary and BCD multiplication ; Binary coded decimals ; Binary multipliers ; Computer arithmetic ; Decimal floating points ; Hardware acceleration ; Hardware implementations ; Multiplier architecture ; Hardware
  8. Source: Microprocessors and Microsystems ; Volume 39, Issue 4-5 , June–July , 2015 , Pages 296-301 ; 01419331 (ISSN)
  9. URL: http://www.sciencedirect.com/science/article/pii/S0141933115000058