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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 48669 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Ejlali, Alireza
- Abstract:
- Technology scaling allows integrating multiple cores onto a single chip to make the mainstream for advanced embedded systems. However, technology scaling is envisaged to aggravate the reliability of on-chip systems due to increasing transient fault rate due to lower voltages and shrinking transistor dimensions that lead to smaller critical charges. Transient faults are typically resulted due to high-energy particle strikes in hardware and manifest as bit flips. Multi-core systems provide a great opportunity to implement reliability mechanisms such as redundant multithreading (RMT) and process level redundancy. Task replication (e.g. RMT) is a well-established technique to achieve high reliability against transient faults. However, replicated executions may increase system power consumption beyond the chip Thermal Design Power (TDP) constraint. TDP is considered as the highest sustainable power that a chip can dissipate before being forced to exploit a performance throttling mechanism, e.g. Dynamic Thermal Management (DTM). If a chip violates its TDP, it automatically restarts or significantly reduces its performance to prevent a permanent damage. Therefore, due to the unwanted system restarts, DTM techniques may not be applicable for the systems that require satisfying strict timing constraints, e.g. hard real-time embedded systems. In this thesis, at first, we illustrate how task replication may increase peak power consumption and consequently may result in a chip TDP violation. Then, we propose a scheme to manage peak power consumption for task replication on multi-core systems. This scheme schedules real-time tasks on core pairs in a multi-core system without violating real-time constraints. The proposed method aims at removing overlaps of peak power of concurrently executing tasks to keep the power consumption below the chip TDP. To do this, considering the tasks’ power traces, at first, we partition the tasks into parts where different parts have different peak power values. Then, we use two different policies for scheduling the partitioned primary and backup tasks. We use the maximum-peak-power-first (MPPF) policy to schedule the primary tasks, and for the backup tasks, we use the maximum-peak-power-last (MPPL) policy. In this way, those parts of a task that consume higher power overlap with the parts of the other tasks that consume lower power. This leads to a smoothly consumed power and results in reduced peak power values. In summary, our proposed scheme tries to spread out the parts of tasks that consume high power over the entire interval before the deadline with the aim of keeping the total peak power below the chip TDP. Our experiments show that our scheme provides up to 50% (on average by 39%) peak power reduction compared to state-of-the-art schemes
- Keywords:
- Fault Tolerance ; Real Time ; Peak Power Consumption ; Power Consumption ; Embedded Real-Time System ; Thermal Design Power
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