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SRAM leakage reduction by row/column redundancy under random within-die delay variation

Goudarzi, M ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/TVLSI.2009.2026048
  3. Publisher: 2010
  4. Abstract:
  5. Share of leakage in total power consumption of static RAM (SRAM) memories is increasing with technology scaling. Reverse body biasing increases threshold voltage (Vth), which exponentially reduces subthreshold leakage, but it increases SRAM access delay. Traditionally, when all cells of an SRAM block used to have almost the same delay, within-die variations are increasingly widening the delay distribution of cells even within a single SRAM block, and hence, most of these cells are substantially faster than the delay set for the entire block. Consequently, after the reverse body biasing and the resulting delay rise, only a small number of cells violate the original delay of the SRAM block; we propose to replace them with sufficient number of spare rows/columns of SRAM. Our experiments show that the leakage can be reduced by up to 40% in a 90-nm predictive technology by adding less than ten spare columns to an 8-kB SRAM array for a negligible penalty in delay, dynamic power, and area in the presence of 3% uncorrelated random delay variation
  6. Keywords:
  7. Cache memories ; within-die variation ; Access delay ; Delay distributions ; Delay variation ; Dynamic Power ; Process Variation ; Random delay ; Reverse body biasing ; SRAM leakage ; Static RAM (SRAM) chips ; Sub-threshold leakage ; Technology scaling ; Total power consumption ; Within dies ; Within-die variations ; Cache memory ; Dies ; Leakage currents ; Quality assurance ; Redundancy ; Time delay ; Static random access storage
  8. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 18, Issue 12 , 2010 , Pages 1660-1671 ; 10638210 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/5256337